• Journal of IKEEE
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• v.5 no.1 s.8
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• pp.24-34
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• 2001

IP address lookup is a major bottleneck of IP packet processing in high speed router. Existing IP lookup methods are focused only on lookup throughput without considering lookup table update. So their slow update can lead to lookup blocking or wrong routing decision based on obsolete routes. Especially existing IP lookup methods based on CAM(content addressable memory) have slow update of O(n) cycles in spite of their high throughput and low area complexity In this paper we proposes a new IP address lookup method based on pipelined CAM architecture(PICAM) with fast update of O(1) cycle of lookup table and high throughput and low area complexity.

• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.271-274
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• 2000

This paper reports a very fast lookup scheme for Optical IP racket forwarding. A LD by derived Pattern Generartor generate a optical IP Packet encapsulated by any header of level1 and level2. A high speed Lookup scheme for a forwarding has been implemented by EEPLD with tiny SRAMs for optical internetworking. With SRAM of a 10㎱ access time and ～400kB , the Lookup scheme has achieved very high speed lookup time about 100㎱ for 2 memory accesses

• The KIPS Transactions:PartA
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• v.11A no.5
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• pp.333-340
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• 2004

In order that routers forward a packet to its destination, they perform IP address lookup which determines the next hop according to the packet's destination address. In designing high speed routers, IP address lookup is an important issue. In order to design high speed routers, this paper proposes a parallel IP lookup scheme which consists of several IP lookup engines without any modification of already fabricated indirect IP lookup chipsets. Also, we propose a simple rule for partitioning IP prefix entries In an overall forwarding table among several IP lookup engines. And we evaluate the performance of the proposed scheme in terms of the memory size required for storing lookup information and the number of memory accesses on constructing the forwarding table. With additional hardware logics, the proposed scheme can reduce about 30% of the required memory size and 80% of the memory access counts.

• The KIPS Transactions:PartA
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• v.10A no.5
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• pp.453-462
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• 2003

IP address lookup of router searches and decide proper output link using destination address of IP packet that arrie into router. The IP address lookup is essential part in te development of high-speed router needed to high-speed backbone network as one of bottleneck of router performance. This paper introduces DTC data structure that can support gigabit IP address lookup by dynamic trie compression technique that just uses small memory in conventional Pentium CPU. When make a forwarding table by trie compression, the DTC can dynamically select a size of data structure with considering correlation between table's size and searching speed. Also, when compress the prefix trie, DTC makes IP address lookup on the forwarding table of a search on the high speed SRAM cache by minimizing the size of data structure reflecting the structure of the trie. In the experiment result, the DTC data structure recorded performance of maximum $12.5{\times}10^5$ LPS (lookup per second) in conventional Pentium CPU through a dynamic building of most suitable compression over variety of routing tables.

• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.213-216
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• 2000

In this paper, we propose a new scheme which improves the IP address lookup time. The new scheme is composed of two core technologies, named the prefix alignment and the prefix distance ordering. Now, as the Internet is being used commonly by improving the data transmission capacity, the need for enlarging the bandwidth of the Internet is on the rise. IP address lookup performance problem is an important obstacle in the router executing high speed packet forwarding. This results from the fact that the prefixes routing table is composed of and the traffic being processed in unit time are largely on the increase. The proposed lookup scheme is divided into two parts in technology, the one is the algorithm forming a routing database(routing table), the other is the lookup procedure in the actual packet processing.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.5
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• pp.345-353
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• 2003

When designing network processors or implementing network equipments such as routers are implemented, IP lookup operations cause the major impact on their performance. As the organization of the IP address becomes simpler, the speed of the IP lookup operations can go faster. However, since the efficient management of IP address is inevitable due to the increasing number of network users, the address organization should become more complex. Therefore, for both IPv4(IP version 4) and IPv6(IP version 6), it is the essential fact that IP lookup operations are difficult and tedious. Lots of researcher for improving the performance of IP lookups have been presented, but the good solution has not been came out. Software approach alleviates the memory usage, but at the same time it si slow in terms of searching speed when performing an IP lookup. Hardware approach, on the other hand, is fast, however, it has disadvantages of producing hardware overheads and high memory usage. In this paper, conventional researches on IP lookups are shown and their advantages and disadvantages are explained. In addition, by mixing two representative structures, a new hybrid parallel architecture for fast IP lookups is proposed. The performance evaluation result shows that the proposed architecture provides better performance and lesser memory usage.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.11C
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• pp.1171-1177
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• 2002

In this paper, we proposed a high speed IP(Internet Protocol) packet forwarding engine of ATM(Asynchronous Transfer Mode) based label edge routers for POS(Packet over SONET) interface. The forwarding engine uses TCAM(Ternary Content Addressable Memory) for high performance lookup processing of the packet received from POS interface. We have accomplished high speed IP packet forwarding in hardware by implementing the functions of high speed IP header Processing and lookup control into FPGA(Field Programmable Gate Array). The proposed forwarding engine has the functions of label edge routers as the lookup controller supports MPLS(Multiprotocol Label Switching) packet processing functionality.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.3-4
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• 2006

Fast IP address lookup in routers is essential to achieve packet forwarding in wire-speed. The longest prefix matching for IP address lookup is more complex than exact matching because of its dual dimensions, length and value. By thoroughly studying the current proposals for IP address lookup, we find out that the binary search could be a low-cost solution while providing high performance. Most of the existing binary search algorithms based on trie have simple data structures which can be easily implemented, but they have some problems because of empty internal nodes. The proposed algorithm is based on trie structure, but empty internal nodes are replaced by priority prefixes. The best-matching-prefix search in the proposed algorithm is more efficiently performed since search can be finished earlier when input is matched with a priority prefix. The performance evaluation results show that the constructed priority-trie has very good performance in the lookup speed and the scalability.

• The KIPS Transactions:PartC
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• v.10C no.5
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• pp.641-646
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• 2003

Packet processing speed of routers as well as transmission speed of physical links gives a great effect on IP packet transfer rate in Internet. The router forwards a packet after determining the next hop to the packet's destination. IP address lookup is a main design issue for high performance routers. In this paper, we propose a partitioned compressed-trie for speeding-up IP address lookup algorithms based on tie data structure by exploiting path compression. In the ,proposed scheme, IP prefixes are divided into several compressed-tries and lookup is performed on only one partitioned compressed-trie. Memory access time for IP address lookup is lessen due to compression technique and memory required for maintaining partition does not increased.

• The Journal of the Korea Contents Association
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• v.7 no.3
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• pp.50-59
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• 2007

IP address lookup is one of the most important and complex functions in the router. In this paper, we propose an improved technique of LC-trie to increase the performance of IP address lookup in the high performance router. We effectively apply the prefix pruning method, which is used for the compression of the forwarding table in TCAM((Ternary Content Addressable Memory), to the LC-trie. This technique can decrease the number of memory accesses and upgrade the lookup speed. Moreover, through the real forwarding table and the real traffic distribution, we evaluate the performance of our scheme in terms of the lookup time and the number of memory access, comparing with that of the previous LC-trie.