• The Transactions of the Korean Institute of Electrical Engineers A
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• v.52 no.11
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• pp.647-654
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• 2003

As electrical power system has become complicated and enlarged to cope with the increasing electric demand, it has to be expected that higher speed, higher reliability, higher function and higher arithmetic ability in protective relay should be realized. Therefore, in this papers, by hardware design and implementation used DMA controller that transfer blocks of data to any location in the memory map without interfering with CPU operation, CPU utilization is increased effectively, as a result it made possible to implement multi-function digital protective relay which has high trust and high function of protection as well as control and metering for power transformers using single processor(DSP).

• KSCE Journal of Civil and Environmental Engineering Research
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• v.31 no.4D
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• pp.595-601
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• 2011

There is currently applied to the unit cost per a distance (KRW/km) for estimating the conceptual cost of civil work on basic planning stage of high speed railroad. This unit cost is an arithmetic average value based on historical data, which could be in big error. It also is difficult to explain the deficiency comparing the estimated cost derived from next basic design stage. This study provides the conceptual estimation model using by the parametric method and regression analysis. Independent variables are the distance and the geological materials (earth, weathered rock, soft-rock, hard-rock), extracting from the actual data to 36 contracts. The deviation between the unit costs estimated using the developed model and the actual cost data is presented in the range from -0.4% to +31%. This range is acceptable compared the typical range "-30% to + 50%". This model will improve the accuracy of existing method and be expected to contribute to effective total cost management and the economic aspects, reduce the financial expenditure.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.5
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• pp.1-6
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• 2016

Image rotation is one of main pre-processing step in image processing or image pattern recognition. It is implemented with rotation matrix multiplication. However it requires lots of floating point arithmetic operations and trigonometric function calculations, so it takes long execution time. We propose a new high speed image rotation algorithm without two major time-consuming operations. It use just 2 shear translation operations, so it is very fast. In addition, we apply a parallel computing technique with CUDA. CUDA is a massively parallel computing architecture using prevailed GPU recently. As GPU is a dedicated graphic processor, it is exellent for parallel processing of pixels. We compare the proposed algorithm with the conventional rotation one with various size images. Experimental results show that the proposed algorithm is superior to the conventional rotation ones.

• Journal of Advanced Navigation Technology
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• v.18 no.6
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• pp.600-608
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• 2014

In this paper, CABAC H/W module is developed using co-design method. After entire H.264/AVC encoder was developed with C using reference SW(JM), CABAC H/W IP is developed as a block in H.264/AVC encoder. Context modeller of CABAC is included on the hardware to update the changed value during binary encoding, which enables the efficient usage of memory and the efficient design of I/O stream. Hardware IP is co-operated with the reference software JM of H.264/AVC, and executed on Virtex-4 FX60 FPGA on ML410 board. Functional simulation is done using Modelsim. Compared with existing H/W module of CABAC with register-level design, the development time is reduced greatly and software engineer can design H/W module more easily. As a result, the used amount of slice in CABAC is less than 1/3 of that of CAVLC module. The proposed co-design method is useful to provide hardware accelerator in need of speed-up of high efficient video encoder in embedded system.

• Journal of IKEEE
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• v.18 no.3
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• pp.356-361
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• 2014

This paper proposes hardware architecture of HEVC (high efficiency video coding) CABAC (context-based adaptive binary arithmetic coding) binarizer. The proposed binarizer was designed and implemented as an independent module that can be integrated into HEVC CABAC encoder. It generates each bin string of each syntax element in a single cycle. It consists of controller module, TU (truncated unary binarization) module, TR (truncated Rice binarization) module, FL (fixed length binarization) module, EGK (k-th order exp-Golomb coding) module, CALR (coeff_abs_level_remaining) module, QP Delta (cu_qp_delta_abs) module, Intra Pred (intra_chroma_pred_mode) module, Inter Pred (inter_pred_idc) module, and Part Mode (part_mode) module. The proposed binarizer was designed in Verilog HDL, and it was implemented in 45 nm technology. Its operating speed, gate count, and power consumption are 200 MHz, 1,678 gates, and 50 uW, respectively.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.589-592
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• 2004

The CORDIC algorithm can be implemented very simple H/W, but needs a lot of latency to compute trigonometric function. The RA(Redundant Arithmetic) resolves this problem, but also has difficulty to determine the directions of micro-rotations. The pre-computed direction of micro-rotation algorithm relieves the RA of this matter. In this paper, we proposed the modified the pre-computed algorithm adopted with a table-lookup. Instead of reducing H/W complexity, its performance and calculation errors are improved.

• Proceedings of the KAIS Fall Conference
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• 2010.11a
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• pp.138-141
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• 2010

본 논문에서는 고안전성 연산제어 장치의 열차제어시스템에 대한 적용성을 평가하여 그 결과를 분석하였다. 고안전성 연산제어 장치의 적용대상으로 열차제어시스템에서 가장 대표적인 지상 ATP 시스템을 선정하였다. 지상 ATP(Automatic Train Protection) 시스템은 다수의 차상 ATP 시스템과 통신하여 각 열차의 위치를 확인하고, 각 열차마다 안전 운행에 필요한 정보이동허가, 제한 속도 등의 열차정보를 전송하는 열차제어시스템의 하나이다. 적용대상 열차제어시스템(지상 ATP)의 고안전성 연산처리 장치의 평가항목으로 입력처리시간, 보팅 성공률, 보팅 용량, 최대 입력처리 개수를 정하였으며, DSV보드 LVDS 전송성능, DSV 메모리 공유 및 보팅성능, 최대 입력처리성능 및 보팅성공률을 시험하여 고안전성 연산처리장치의 적용성을 평가였다.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.8
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• pp.1449-1455
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• 2010

The excitation control system of an emergency diesel generator is classified as a kind of safety-related system. Compared with other control systems in a power plant, this system is required to be more reliable and have better performance. In this paper, the digital multi-redundant excitation system for a diesel generator was proposed. The signal processing system of the proposed system makes high speed signal processing and arithmetic in excitation control possible. The improved soft start algorithm and multiple PI parameters adaptation considering the diesel generator characteristics were implemented in the proposed system. The developed system was applied to a nuclear power plant successfully.

• Proceedings of the KIEE Conference
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• 2005.07d
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• pp.2967-2969
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• 2005

2003년에 영상압축의 표준으로 제시된 H.264/AVC의 압축성능은 대부분 Context-based Adaptive Binary Arithmetic Codes (CAHAC)라는 새로운 엔트로피 코딩에 기인한 것이다. 그러나, CABAC의 뛰어난 성능에도 불구하고 복잡한 처리과정 때문에 하드웨어로 구현하기가 상당히 곤란하다. 곱셈기가 없는 알고리즘임에도 불구하고 영역(range), 오프셋(offset), 그리고 컨텍스트 변수들(context varivales)을 순차적으로 구해야 하기 때문이다. 이 논문에서는 한번에 최대 두 비트를 디코딩 할 수 있는 예측기법을 통하여 CARAC의 전체적인 디코딩 시간을 줄일 수 있는 방법을 제안한다. 한 비트를 디코딩하기 위해서는 두 개의 심볼(a set of binary symbols)에 대한 확률분포를 사전에 알아야 하지만, 제안된 방법에서는 두 비트를 동시에 디코딩할 수 있도록 네 개의 심볼(two sets of binary symbols)에 대한 확률 분포를 예측하여 디코더에 제공한다. 제안된 예측기법을 CABAC 디코더에 적용한 결과, 기존보다 10-13%의 복호시간을 단축하는 효과를 가졌다. 논문에서 제안된 예측기법을 통한 고속디코더의 구현은 확률을 기반으로 하는 신호처리에 사용되어 고속의 시스템을 구성하는데 효과적으로 적용될 수 있다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.8C
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• pp.812-818
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• 2002

반도체 기술과 멀티기디어 통신기술이 발달하면서 고품위의 영상과 다중 채널의 오디오에 관심을 갖게되었다. 특히 DVD 시장의 급성장으로 인하여 고품질의 영상 및 오디오 필요성이 중요한 기술로 대두되었다. MPEG-Audio 표준안은 어떠한 비트율도 지원한다. 본 논문에서는 MPEG-Audio의 핵심부분인 필터부분을 DALUT (Distributed Arithmetic Look-Up Table)방식을 사용하여 FPGA(Field Programmable Gate Array)에 구현하였다. 고속 필터를 설계하기 위해서 승산기 대신에 DALUT를 사용하였으며 최소 10㎒에서 최대 30㎒ 사이에서 동작한다. 본 논문의 설계는 모두 VHDL로 구현하였으며, 알고리즘 검증은 C언어를 사용하였다. VHDL의 시뮬레이션은 ALDEC사의 Active-HDL5.1과 Synopsys사의 vhdlsim을 사용하였고, 합성은 Synopsys사의 design-analyzer를 사용하였다. 타겟 라이브러리는 XILINX사의 XC4010E, XC4020EX, XC4052XL을 사용하였으며, P＆R 툴은 XACT Ml.4를 사용하였다.