• Journal of Power Electronics
• /
• 제11권5호
• /
• pp.655-661
• /
• 2011

This paper presents two topologies for single-stage single-phase double-buck type PFC converters, designed to operate at high power factor, near sinusoidal input currents and adjustable output voltage. Unlike the known buck type PFC topologies, in which the output voltage is always lower than the maximum input voltage, the proposed converters can operate at output voltages higher than the ac input peak voltage. A reduced number of switches on the main path of the current are another characteristic of the two proposed topologies. To shape the input line currents, a fast and robust controller based on a sliding mode approach is proposed. This active non-linear control strategy, applied to these converters allows high quality input currents. A Proportional Integral (PI) controller is adopted to regulate the output voltage of the converters. This external voltage controller modulates the amplitude of the sinusoidal input current references. The performances of the presented rectifiers are verified with experimental results.

• 조명전기설비학회논문지
• /
• 제29권3호
• /
• pp.69-80
• /
• 2015

This paper is writing about developing magnet power supply. It is very important for power supply to obtain output current in high precision and high stability. As a switching noise and a power noise are the cause of disrupting the stability of output current, to remove these at the front end, low pass filter with 300Hz cutoff frequency is designed and placed. And also to minimize switching noise of the current into magnet and to stop abrupt fluctuations, output filter should be designed, when doing this, we design it by considering load has high value inductance. As power supply demands the stability of less than 5ppm, high precision 24bit(300nV/bit) analog digital converter is needed. As resolving power of 24bit(300nV/bit) analog digital converter is high, it is also very important to design the input stage of analog digital converter. To remove input noise, 4th order low pass filter is composed. Due to the limitation of clock, to minimize quantization error between 15bit DPWM and output of ADC having 24bit resolving power, ${\Sigma}-{\Delta}$ modulation is used and bit contracted DPWM is constituted. And before implementing, to maximize efficiency, simulink is used.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제15권4호
• /
• pp.437-444
• /
• 2015

A high output power voltage controlled oscillator (VCO) in the U-band was implemented using a 65 nm CMOS process. The proposed VCO used a transmission line to increase output voltage swing and overcome the limitations of CMOS technologies. Two varactor banks were used for fine tuning with a 5% frequency tuning range. The proposed VCO showed small variation in output voltage and operated at 51.55-54.18 GHz. The measured phase noises were -51.53 dBc/Hz, -91.84 dBc/Hz, and -101.07 dBc/Hz at offset frequencies of 10 kHz, 1 MHz, and 10 MHz, respectively, with stable output power. The chip area, including the output buffer, is $0.16{\times}0.16mm^2$ and the maximum output power was -0.11 dBm. The power consumption was 33.4 mW with a supply voltage of 1.2-V. The measured $FOM_P$ was -190.8 dBc/Hz.

• Journal of Power Electronics
• /
• 제19권3호
• /
• pp.665-675
• /
• 2019

Renewable energy based on photovoltaic systems is beginning to play an important role to supply power to remote areas all over the world. Owing to the lower output voltage of photovoltaic arrays, high gain DC-DC converters with a high efficiency are required in practice. This paper presents a novel interleaved DC-DC boost converter with a high voltage gain, where the input terminal is interlaced in parallel and the output terminal is staggered in series (IPOSB). The IPOSB configuration can reduce input current ripples because two inductors are interlaced in parallel. The double output capacitors are charged in staggered parallel and discharged in series for the load. Therefore, IPOSB can attain a high step-up conversion and a lower output voltage ripple. In addtion, the output voltage can be automatically divided by two capacitors, without the need for extra sharing control methods. At the same time, the voltage stress of the power devices is lowered. The inrush current problem of capacitors is restrained by the inductor when compared with high gain converters with a switching-capacitor structure. The working principle and steady-state characteristics of the converter are analyzed in detail. The correctness of the theoretical analysis is verified by experimental results.

• Journal of Power Electronics
• /
• 제13권1호
• /
• pp.20-30
• /
• 2013

This paper presents a soft switching DC/DC converter for high voltage application. The interleaved pulse-width modulation (PWM) scheme is used to reduce the ripple current at the output capacitor and the size of output inductors. Two converter cells are connected in series at the high voltage side to reduce the voltage stresses of the active switches. Thus, the voltage stress of each switch is clamped at one half of the input voltage. On the other hand, the output sides of two converter cells are connected in parallel to achieve the load current sharing and reduce the current stress of output inductors. In each converter cell, a half-bridge converter with the asymmetrical PWM scheme is adopted to control power switches and to regulate the output voltage at a desired voltage level. Based on the resonant behavior by the output capacitance of power switches and the transformer leakage inductance, active switches can be turned on at zero voltage switching (ZVS) during the transition interval. Thus, the switching losses of power MOSFETs are reduced. The current doubler rectifier is used at the secondary side to partially cancel ripple current. Therefore, the root-mean-square (rms) current at output capacitor is reduced. The proposed converter can be applied for high input voltage applications such as a three-phase 380V utility system. Finally, experiments based on a laboratory prototype with 960W (24V/40A) rated power are provided to demonstrate the performance of proposed converter.

• Journal of Power Electronics
• /
• 제15권4호
• /
• pp.1131-1138
• /
• 2015

This study presents an input-powered high-efficiency interface circuit for energy harvesting systems, and introduces a zero standby power design to reduce power consumption significantly while removing the external power supply. This interface circuit is composed of two stages. The first stage voltage doubler uses a positive feedback control loop to improve considerably the conversion speed and efficiency, and boost the output voltage. The second stage active diode adopts a common-grid operational amplifier (op-amp) to remove the influence of offset voltage in the traditional comparator, which eliminates leakage current and broadens bandwidth with low power consumption. The system supplies itself with the harvested energy, which enables it to enter the zero standby mode near the zero crossing points of the input current. Thereafter, high system efficiency and stability are achieved, which saves power consumption. The validity and feasibility of this design is verified by the simulation results based on the 65 nm CMOS process. The minimum input voltage is down to 0.3 V, the maximum voltage efficiency is 99.6% with a DC output current of 75.6 μA, the maximum power efficiency is 98.2% with a DC output current of 40.4 μA, and the maximum output power is 60.48 μW. The power loss of the entire interface circuit is only 18.65 μW, among which, the op-amp consumes only 2.65 μW.

• Journal of Electrical Engineering and Technology
• /
• 제4권1호
• /
• pp.79-86
• /
• 2009

This paper presents a flyback technology in power conversion aimed at increasing efficiency and power density, reducing cost and using minimum components in AC-DC conversion. The proposed converter provides these features for square waveforms and constant frequency PWM. It is designed to operate in a wide input voltage range of 75-265VAC RMS with two output voltages of 5V and 20V respectively and full load output power of 5W. The proposed converter is suitable for high efficiency and high power density application such as LCDs, TV power modules, AC adapters, motor control, appliance control, telecom and networking products.

• 전력전자학회논문지
• /
• 제5권6호
• /
• pp.530-536
• /
• 2000

• Journal of Power Electronics
• /
• 제1권2호
• /
• pp.78-87
• /
• 2001

A new high-power step-up based on the two-module parallel-input (PISO) modular dual inductor-fed push-pull converter is proposed. The proposed converter is operated at a constant duty cycle and employs and auxiliary circuit to control the output voltage with a phase-shift between two modules. It shows a high efficiency due to the greatly reduced switch turn-off stress. It also shows a high and linear voltage conversion ratio, low current stress in the output capacitor, and fast control-to-output dynamics. The operation principles and the mathematical models of the proposed converter are presented. Features of the proposed converter are discussed in comparison with the two-module PISO modular dual inductor-fed push-pull converter. Also, experimental results from a 50kHz, 800W, 350 Vdc prototype with an input voltage range of 20-32 Vdc are provided to confirm the validity of the proposed converter. The new converter compares favorably with the conventional counterpart, and is considered well siuted to high-power step-up applications.

• Journal of Electrical Engineering and Technology
• /
• 제9권2호
• /
• pp.569-575
• /
• 2014

A highly efficient class E power amplifier is demonstrated for application to wireless power transfer system. The amplifier is designed with an L-type matching at the output for harmonic rejection and output matching. The power loss and the effect of each component in the amplifier with the matching circuit are analyzed with the current ratio transmitted to the output load. Inductors with a quality factor of more than 120 are used in a dc feed and the matching circuit to improve transmission efficiency. The single-ended amplifier with 20 V supply voltage shows 7.7 W output power and 90.8% power added efficiency at 6.78 MHz. The wireless power transfer (WPT) system with the amplifier shows 5.4 W transmitted power and 82.3% overall efficiency. The analysis and measurements show that high-Q inductors are required for the amplifier design to realize highly efficient WPT system.