• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.1
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• pp.12-16
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• 2011

In this study, we fabricated the flexible pentacene TFTs with the polymer gate dielectric and contact printing method by using the silver nano particle ink as a source/drain material on plastic substrate. In this experiment, to lower the cross-linking temperature of the PVP gate dielectric, UV-Ozone treatment has been used and the process temperature is lowered to $90^{\circ}C$ and the surface is optimized by various treatment to improve device characteristics. We tried various surface treatments; $O_2$ Plasma, hexamethyl-disilazane (HMDS) and octadecyltrichlorosilane (OTS) treatment methods of gate dielectric/semiconductor interface, which reduces trap states such as -OH group and grain boundary in order to improve the OTFTs properties. The optimized OTFT shows the device performance with field effect mobility, on/off current ratio, and the sub-threshold slope were extracted as $0.63cm^2 V^{-1}s^{-1}$, $1.7{\times}10^{-6}$, and of 0.75 V/decade, respectively.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.9
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• pp.623-627
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• 1999

We report a new in-situ fluorine passivation method without in implantation by employing excimer laser annealing of $SiO_{x}F_{y}$/a-Si structure and its effects on p-channel poly-Si TFTs. The proposed method doesn't require any additional annealing step and is a low temperature process because fluorine passivation is simultaneous with excimer-laser-induced crystallization. A in-situ fluorine passivation by the proposed method was verified form XPS analysis and conductivity measurement. From experimental results, it has been shown that the proposed method is effective to improve the electrical characteristics, specially field-effect mobility, and the electrical stability of p-channel poly-Si TFTs. The improvement id due to fluorine passivation, which reduces the trap state density and forms the strong Si-F bonds in poly-Si channel and $SiO_2/poly-Si$ interface. From these results, the high performance poly-Si TFTs canbe obtained by employing the excimer-laser-induced fluorine passivation method.

• Journal of Electrical Engineering and information Science
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• v.3 no.2
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• pp.239-244
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• 1998

Piezoelectric pressure sensors and pyroelectric infrared detectors based on ZnO thin film have been integrated with GaAs metal-semiconductor field effect transistor (MESFET) amplifiers. Surface micromachining techniques have been applied in a GaAs MESFET process to form both microsensors and electronic circuits. The on-chip integration of microsensors such as pressure sensors and infrared detectors with GaAs integrated circuits is attractive because of the higher operating temperature up to 200 oC for GaAs devices compared to 125 oC for silicon devices and radiation hardness for infrared imaging applications. The microsensors incorporate a 1${\mu}$m-thick sputtered ZnO capacitor supported by a 2${\mu}$m-thick aluminum membrane formed on a semi-insulating GaAs substrate. The piezoelectric pressure sensor of an area 80${\times}$80 ${\mu}$m2 designed for use as a miniature microphone exhibits 2.99${\mu}$V/${\mu}$ bar sensitivity at 400Hz. The voltage responsivity and the detectivity of a single infrared detector of an area 80${\times}$80 $\mu\textrm{m}$2 is 700 V/W and 6${\times}$108cm$.$ Hz/W at 10Hz respectively, and the time constant of the sensor with the amplifying circuit is 53 ms. Circuits using 4${\mu}$m-gate GaAs MESFETs are fabricated in planar, direct ion-implanted process. The measured transconductance of a 4${\mu}$m-gate GaAs MESFET is 25.6 mS/mm and 12.4 mS/mm at 27 oC and 200oC, respectively. A differential amplifier whose voltage gain in 33.7 dB using 4${\mu}$m gate GaAs MESFETs is fabricated for high selectivity to the physical variable being sensed.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.40 no.1
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• pp.114-123
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• 2017

The global small and mid-sized display market is changing from thin film transistor-liquid crystal display to organic light emitting diode (OLED). Reflecting these market conditions, the domestic and overseas display panel industry is making great effort to innovate OLED technology and incease productivity. However, current OLED production technology has not been able to satisfy the quality requirement levels by customers, as the market demand for OLED is becoming more and more diversified. In addition, as OLED panel production technology levels to satisfy customers' requirement become higher, product quality problems are persistently generated in OLED deposition process. These problems not only decrease the production yield but also cause a second problem of deteriorating productivity. Based on these observations, in this study, we suggest TRIZ-based improvement of defects caused by glass pixel position deformation, which is one of quality deterioration problems in small and medium OLED deposition process. Specifically, we derive various factors affecting the glass pixel position shift by using cause and effect diagram and identify radical reasons by using XY-matrix. As a result, it is confirmed that glass heat distortion due to the high temperature of the OLED deposition process is the most influential factor in the glass pixel position shift. In order to solve the identified factors, we analyzed the cause and mechanism of glass thermal deformation. We suggest an efficient method to minimize glass thermal deformation by applying the improvement plan of facilities using contradiction matrix in TRIZ. We show that the suggested method can decrease the glass temperature change by about 23% through an experiment.

• Korean Journal of Metals and Materials
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• v.46 no.11
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• pp.762-769
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• 2008

Hydrogenated amorphous silicon(a-Si : H) layers, 120 nm and 50 nm in thickness, were deposited on 200 $nm-SiO_2$/single-Si substrates by inductively coupled plasma chemical vapor deposition(ICP-CVD). Subsequently, 30 nm-Ni layers were deposited by E-beam evaporation. Finally, 30 nm-Ni/120 nm a-Si : H/200 $nm-SiO_2$/single-Si and 30 nm-Ni/50 nm a-Si:H/200 $nm-SiO_2$/single-Si were prepared. The prepared samples were annealed by rapid thermal annealing(RTA) from $200^{\circ}C$ to $500^{\circ}C$ in $50^{\circ}C$ increments for 30 minute. A four-point tester, high resolution X-ray diffraction(HRXRD), field emission scanning electron microscopy (FE-SEM), transmission electron microscopy (TEM), and scanning probe microscopy(SPM) were used to examine the sheet resistance, phase transformation, in-plane microstructure, cross-sectional microstructure, and surface roughness, respectively. The nickel silicide on the 120 nm a-Si:H substrate showed high sheet resistance($470{\Omega}/{\Box}$) at T(temperature) < $450^{\circ}C$ and low sheet resistance ($70{\Omega}/{\Box}$) at T > $450^{\circ}C$. The high and low resistive regions contained ${\zeta}-Ni_2Si$ and NiSi, respectively. In case of microstructure showed mixed phase of nickel silicide and a-Si:H on the residual a-Si:H layer at T < $450^{\circ}C$ but no mixed phase and a residual a-Si:H layer at T > $450^{\circ}C$. The surface roughness matched the phase transformation according to the silicidation temperature. The nickel silicide on the 50 nm a-Si:H substrate had high sheet resistance(${\sim}1k{\Omega}/{\Box}$) at T < $400^{\circ}C$ and low sheet resistance ($100{\Omega}/{\Box}$) at T > $400^{\circ}C$. This was attributed to the formation of ${\delta}-Ni_2Si$ at T > $400^{\circ}C$ regardless of the siliciation temperature. An examination of the microstructure showed a region of nickel silicide at T < $400^{\circ}C$ that consisted of a mixed phase of nickel silicide and a-Si:H without a residual a-Si:H layer. The region at T > $400^{\circ}C$ showed crystalline nickel silicide without a mixed phase. The surface roughness remained constant regardless of the silicidation temperature. Our results suggest that a 50 nm a-Si:H nickel silicide layer is advantageous of the active layer of a thin film transistor(TFT) when applying a nano-thick layer with a constant sheet resistance, surface roughness, and ${\delta}-Ni_2Si$ temperatures > $400^{\circ}C$.

• Resources Recycling
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• v.24 no.1
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• pp.58-65
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• 2015

Although Korea is a top market sharing and world leading producer and developer of flat panel display devices, relevant recycling technology is not up to her prestigious status. Besides, most of the waste glass arising from flat panel displays is currently land-filled. The present paper mainly reviews on development of recycling systems for waste TFT-LCD glass from end-of-life LCD TVs and monitors and TFT-LCD process waste of crushed glass particles with target end uses of raw material for high strength concrete pile and glass fibers, respectively. Waste LCD glass was recycled to fabricate ingredients for high strength concrete piles with enhanced physical properties and spherical foam products. The waste LCD glass recycling technology is already developed to fabricate long and short fibers at commercial level. In view of these, future R & D on waste LCD glass materials is to be directed toward implementation of commercial materials recycling system therefrom.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.3
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• pp.7-11
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• 2011

In this paper, we proposed a simple and high-yield printing process for source and drain electrodes of organic thin film transistor (OTFT). The surface energy of PVP (poly 4-vinylphenol) gate dielectric was decreased from 56 $mJ/m^2$ to 45 $mJ/m^2$ by adding fluoride of 3000ppm into it. Meanwhile the surface energy of source and drain (S/D) electrodes area on the PVP was increased to 87 $mJ/m^2$ by treating the areas, which was patterned by photolithography, with oxygen plasma, maximizing the surface energy difference from the other areas. A conductive polymer, G-PEDOT:PSS, was deposited on the S/D electrode areas by brushing painting process. With such a simple process we could obtain a high yield of above 90 % in $16{\times}16$ arrays of OTFTs. The performance of OTFTs with the fluoride-added PVP was similar to that of OTFTs with the ordinary PVP without fluoride, generating the mobility of 0.1 $cm^2/V.sec$, which was sufficient enough to drive electrophoretic display (EPD) sheet. The EPD panel employing the OTFT-backpane successfully demonstrated to display some patterns on it.