• Proceedings of the KSME Conference
• /
• 2003.11a
• /
• pp.1932-1938
• /
• 2003

We have applied spectroscopic ellipsometry to investigate $high-{\kappa}$ dielectric thin films and correlate their optical properties with fabrication processes, in particular, with high temperature annealing. The use of high-k dielectrics such as $HfO_{2}$, $Ta_{2}O_{5}$, $TiO_{2}$, and $ZrO_{2}$ as the replacement for $SiO_{2}$ as the gate dielectric in CMOS devices has received much attention recently due to its high dielectric constant. From the characteristics found in the pseudo-dielectric functions or the Tauc-Lorentz dispersions, the optical properties such as optical band gap, polycrystallization, and optical density will be discussed.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.1 no.2
• /
• pp.103-110
• /
• 2001

Gate oxide scaling for sub-l00nm CMOS devices has been studied. Issues on the gate oxide scaling are reviewed, which are boron penetration, reliability, and direct tunneling leakage currents. Reliability of Sub-2.0nm oxides and the device performance degradation due to boron penetration are investigated. Especially, the effect of gate leakage currents on the transistor characteristics is studied. As a result, it is proposed that thinner oxides than previous expectations may be usable as scaling proceeds. Based on the gate oxide thickness optimization process we have established, high performance CMOS transistors of $L_{gate}=70nm$ and $T_{ox}=1.4nm$ were fabricated, which showed excellent current drives of $860\mu\textrm{A}/\mu\textrm{m}$ (NMOS) and $350\mu\textrm{A}/\mu\textrm{m}$ (PMOS) at $I_{off}=10\mu\textrm{A}/\mu\textrm{m}$ and $V_dd=1.2V$, and CV/I of 1.60ps (NMOS) and 3.32ps(PMOS).

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2003.07a
• /
• pp.428-431
• /
• 2003

In this paper, the stress induced leakage currents of thin silicon oxides is investigated in the ULSI implementation with nano structure transistors. The stress and transient currents associated with the on and off time of applied voltage were used to measure the distribution of high voltage stress induced traps in thin silicon oxide films. The stress and transient currents were due to the charging and discharging of traps generated by high stress voltage in the silicon oxides. The transient current was caused by the tunnel charging and discharging of the stress generated traps nearby two interfaces. The stress induced leakage current will affect data retention in electrically erasable programmable read only memories. The oxide current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between $113.4{\AA}$ and $814{\AA}$, which have the gate area 10-3cm2. The stress induced leakage currents will affect data retention and the stress current, transient current is used to estimate to fundamental limitations on oxide thicknesses.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.3 no.1
• /
• pp.13-20
• /
• 2003

Both MgO and $Sc_2O_3$ are shown to provide low interface state densities (in the $10^{11}{\;}eV^{-1}{\;}cm{\;}^{-2}$ range)on n-and p-GaN, making them useful for gate dielectrics for metal-oxide semiconductor(MOS) devices and also as surface passivation layers to mitigate current collapse in GaN/AlGaN high electron mobility transistors(HEMTs).Clear evidence of inversion has been demonstrated in gate-controlled MOS p-GaN diodes using both types of oxide. Charge pumping measurements on diodes undergoing a high temperature implant activation anneal show a total surface state density of $~3{\;}{\times}{\;}10^{12}{\;}cm^{-2}$. On HEMT structures, both oxides provide effective passivation of surface states and these devices show improved output power. The MgO/GaN structures are also found to be quite radiation-resistant, making them attractive for satellite and terrestrial communication systems requiring a high tolerance to high energy(40MeV) protons.

• Korean Journal of Materials Research
• /
• v.1 no.3
• /
• pp.125-131
• /
• 1991

Boron penetration phenomenon of $p^{+}$ silicon gate with as-deposited amorphous or polycrystalline Si upon high temperature annealing was investigated using high frequency C-V (Capacitance-Volt-age) analysis, CCST(Constant Current Stress Test), TEM(Transmission Electron Microscopy) and SIMS(Secondary Ion Mass Spectroscopy), C-V analysis showed that an as-deposited amorphous Si gate resulted in smaller positive shifts in flatband voltage compared wish a polycrystalline Si gate, thus giving 60-80 percent higher charge-to-breakdown of gate oxides. The reduced boron penetration of amorphous Si gate may be attributed to the fewer grain boundaries available for boron diffusion into the gate oxide and the shallower projected range of $BF_2$ implantation. The relation between electron trapping rate and flatband voltage shift was also discussed.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2010.06a
• /
• pp.371-371
• /
• 2010

In this paper, the stress induced leakage currents of thin silicon oxides is investigated in the MEMS implementation with nano structure. The stress and transient currents associated with the on and off time of applied voltage were used to measure the distribution of high voltage stress induced traps in thin silicon oxide films. The oxide current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between $41{\AA}$, which have the gate area $10^{-3}cm^2$. The stress current, transient current is used to estimate to fundamental limitations on oxide thicknesses.

• Journal of the Microelectronics and Packaging Society
• /
• v.15 no.4
• /
• pp.25-29
• /
• 2008

Reliability and performance in metal gate/high-k device with multiple gate dielectrics were investigated. MOSFETs with a thin $HfSiO_x$ layer on a thermal Si02 dielectric as gate dielectrics exhibit excellent mobility and low interface trap density. However, the distribution of threshold voltages of $HfSiO_x/SiO_2$ stack devices were wider than those of $SiO_2$ and $HfSiO_x$ single layer devices due to the penetration of Hf and/or intermixing of $HfSiO_x$ with underlying $SiO_2$. The results of TZDB and SILC characteristics suggested that a certain portion of $HfSiO_x$ layer reacted with the underlying thick $SiO_2$ layer, which in turn affected the reliability characteristics.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2006.08a
• /
• pp.533-536
• /
• 2006

VIATRON TECHNOLOGIES has developed Field-Enhanced Rapid Thermal Processor (FERTP) system that enables LTPS LCD and AMOLED manufacturers to produce poly-Si films at low cost, high throughput, and high yield. The FE-RTP allows the diverse process options including crystallization, thermal oxidation of gate oxides and fast pre-compactions. The process and equipment compatibility with a-Si TFT lines is able to provide a viable solution to produce poly-Si TFTs using a-Si TFT lines.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.10 no.3
• /
• pp.203-212
• /
• 2010

In this paper, we present an analytical model for the first eigen energy level ($E_0$) of the carriers in the inversion layer in present generation MOSFETs, having ultrathin gate oxides and high substrate doping concentrations. Commonly used approaches to evaluate $E_0$ make either or both of the following two assumptions: one is that the barrier height at the oxide-semiconductor interface is infinite (with the consequence that the wave function at this interface is forced to zero), while the other is the triangular potential well approximation within the semiconductor (resulting in a constant electric field throughout the semiconductor, equal to the surface electric field). Obviously, both these assumptions are wrong, however, in order to correctly account for these two effects, one needs to solve Schrodinger and Poisson equations simultaneously, with the approach turning numerical and computationally intensive. In this work, we have derived a closed-form analytical expression for $E_0$, with due considerations for both the assumptions mentioned above. In order to account for the finite barrier height at the oxide-semiconductor interface, we have used the asymptotic approximations of the Airy function integrals to find the wave functions at the oxide and the semiconductor. Then, by applying the boundary condition at the oxide-semiconductor interface, we developed the model for $E_0$. With regard to the second assumption, we proposed the inclusion of a fitting parameter in the wellknown effective electric field model. The results matched very well with those obtained from Li's model. Another unique contribution of this work is to explicitly account for the finite oxide-semiconductor barrier height, which none of the reported works considered.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.7
• /
• pp.23-31
• /
• 2008

Experiment results are presented for gate oxide degradation under the constant voltage stress conditions using MOSFETs with 3-nm-thick gate oxides that are treated by deuterium gas. Two kinds of methods, annealing and implantation, are suggested for the effective deuterium incorporation. Annealing process was rather difficult to control the concentration of deuterium. Because the excess deuterium in gate oxide could be a precursor for the wear-out of gate oxide film, we found annealing process did not show improved characteristics in device reliability, compared to conventional process. However, deuterium implantation at the back-end process was effective method for the deuterated gate oxide. Device parameter variations as well as the gate leakage current depend on the deuterium concentration and are improved by low-energy deuterium implantation, compared to those of conventional process. Especially, we found that PMOSFET experienced the high voltage stress shows a giant isotope effect. This is likely because the reaction between "hot" hole and deuterium is involved in the generation of oxide trap.