• Journal of the Korean Ceramic Society
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• v.27 no.6
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• pp.741-746
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• 1990

Dielectrics which do not lose their high insulation resistance in reducing atmosphere are necessary for multilayer ceramic capacitors with Ni internal electrode. In this study we investigated the Ca ion site occupancy in A-site excess Ca-doped BaTiO3 by measuring the insulation resistance, lattice constant and Curie temperature. Its Curie temperature, which was lower than that of the pure BaTiO3, was more lowered by sintering in reducing atmosphere. Lattice constnat of c-axis decreased and that of a-axis increased, suggesting substitution of Ca ions for Ti ions. Hence CaTi" acts as an acceptor to maintain high insulation resistance.ance.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.4
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• pp.159-164
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• 2016

In or to generate high electric power in increasing demand, power station should operate facilities to meet requirement. The scale of electric power equipment is increasing in both size and complexity. With unexpected accidents at power facilities or power stations happening, substantial socioeconomic losses in an industrial society is caused. A major cause of unexpected accidents is deterioration of dielectrics, isolating two conductors electrically. In order to detect the deterioration processes of power cables, the operation status of power cables should be monitored on a regular basis. We have invented and installed equipment at Korea Western Power Co., Ltd., located in Taean, in order to predict and prevent the deterioration status of dielectrics destruction of power cables. The main line in Y-connection to the secondary coils of transformer delivers electric power to the external devices. The equipment we developed is the one measuring insulation resistance of cables operation in on/off status with respect to the main line. We present the equipment in terms of operation and configuration of hardware side.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.6
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• pp.466-468
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• 2009

The metal-insulator-silicon (MIS) capacitors with $SiO_2$ and high-k dielectrics ($HfO_2$, $Al_2O_3$) were fabricated, and the current-voltage characteristics were investigated. Especially, an effective barrier height between metal gate and dielectric was extracted by using Fowler-Nordheim (FN) plot and Direct Tunneling (DT) plot of quantum mechanical(QM) modeling. The calculated barrier heights of thermal $SiO_2$, ALD $SiO_2$, $HfO_2$ and $Al_2O_3$ are 3.35 eV, 0.6 eV, 1.75 eV, and 2.65 eV, respectively. Therefore, the performance of non-volatile memory devices can be improved by using engineered tunnel barrier which is considered effective barrier height of high-k materials.

• Journal of Electrical Engineering and Technology
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• v.9 no.2
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• pp.649-654
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• 2014

In this paper, an analytical model for Surrounding Gate (SG) metal-oxide- semiconductor field effect transistors (MOSFETs) considering quantum effects is presented. To achieve this goal, we have used variational approach for solving the Poission and Schrodinger equations. This model is developed to provide an analytical expression for inversion charge distribution function for all regions of device operation. This expression is used to calculate the other important parameters like inversion charge density, threshold voltage, drain current and gate capacitance. The calculated expressions for the above parameters are simple and accurate. This paper also focuses on the gate tunneling issue associated with high dielectric constant. The validity of this model was checked for the devices with different dimensions and bias voltages. The calculated results are compared with the simulation results and they show good agreement.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.3
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• pp.180-184
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• 2002

In this paper, the electrical properties of PVD Ta and $TaN_x$ gate electrodes on $SiO_2$ and their thermal stabilities are investigated. The results show that the work functions of $TaN_x$ gate electrode are modified by the amount of N, which is controlled by the flow rate of $N_2$during reactive sputtering process. The thermal stability of Ta and $TaN_x$ with RTO-grown $SiO_2$ gate dielectrics is examined by changes in equivalent oxide thickness (EOT), flat-band voltage ($V_{FB}$), and leakage current after post-metallization anneal at high temperature in $N_2$ambient. For a Ta gate electrode, the observed decrease in EOT and leakage current is due to the formation of a Ta-incorporated high-K layer during the high temperature annealing. Less change in EOT and leakage current is observed for $TaN_x$ gate electrode. It is also shown that the frequency dispersion and hysteresis of high frequency CV curves are improved significantly by a post-metallization anneal.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.63 no.1
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• pp.80-84
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• 2014

The discharge characteristics of Surface Dielectric Barrier Discharge (SDBD) reactor are investigated to find optimal driving condition with adjusting various parameter. When the high voltage with sine wave form is applied to SDBD source, successive pulsed current waveforms are observed owing to multiple ignitions through the long discharge channel and wall charge accumulation on the dielectric surface. The discharge voltage, total charge between dielectrics, mean energy and power are calculated from measured current and voltage according to electrode gap and dielectric thickness. Discharge mode transition from filamentary to diffusive glow is observed for narrow gap and high applied voltage case. However, when the diffusive discharge is occurred with high applied voltage, the actual firing voltage is always lower than that with low driving voltage. The $Si_3N_4$, $MgF_2$, $Al_2O_3$ and $TiO_2$ are considered for dielectric protection and high secondary electron emission coefficient. SDBD with $MgF_2$ shows the lowest breakdown voltage. $MgF_2$ thin film is proposed as a protection layer for low voltage atmospheric dielectric barrier discharge devices.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.97-98
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• 2009

Tunneling barrier engineered charge trap flash (TBE-CTF) memory capacitor were fabricated using the tunneling barrier engineering technique. Variable oxide thickness (VARIOT) barrier and CRESTED barrier consisting of thin $SiO_2$ and $Si_3N_4$ dielectrics layers were used as engineered tunneling barrier. The charge trapping characteristic with different metal gates are also investigated. A larger memory window was achieved from the TBE-CTF memory with high workfunction metal gate.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.461-463
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• 2009

We report on the fabrication of ZnO-based thin-film transistor (TFT) inverters with top and bottom gate structures with $Al_2O_3$ dielectrics grown by atomic layer deposition (ALD). Since the top gate ZnO-based TFT showed somewhat lower field effect mobility than that of the bottom gate device, our ZnO-based TFT inverters were designed with identical dimensions for both channels. This TFT inverter device demonstrated an high voltage gain at a low supply voltage of 5 V and clear dynamic behavior.

• Proceedings of the KIEE Conference
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• 1994.07b
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• pp.1463-1465
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• 1994

The electrical characteristics of $Al/Ta_2O_5/Si$ metal-oxide-semiconductor (MOS) capacitors were studied. $Ta_2O_5$ films on p-type silicon had been prepared by ionized cluster beam epitaxy technique (ICBE). This $Ta_2O_5$ films have low leakage current, high breakdown strength and low flat band shift. In this research, a single crystalline cpitaxial film of $Ta_2O_5$ has been grown on p-Si wafer using an ICBE technique. The native oxide layer ($SiO_2$) on the silicon substrate was removed below $500^{\circ}C$ by use of an accelerated arsenic ion beam, instead of a high temperature deposition. $Ta_2O_5$ films formed by ICBE technique can be received considerable attention for applications to coupling capacitors, gate dielectrics in MOS devices, and memory storage capacitor insulator because of their high dielectric constants above 20 and low temperature process.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1305-1307
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• 2007

We show that the electrical properties of organic thinfilm transistors(OTFTs) can be enhanced by controlling the morphology of interface between screen printed electrodes and gate dielectrics. Modified surface of the insulator layer($SiO_2$) affect on the interface energy of electrode on $SiO_2$ layer. Contact angle measurement and FT-IR spectrum shows that the interface is properly modified. OTFTs device with high efficiency has been realized through modification of interface layer.