• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.147-148
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• 2006

Ge nanocrystals(NCs)-embedded MOS capacitors are charactenzed in this work using capacitance-voltage measurement. High-k dielectrics $HfO_2$ are employed for the gate material m the MOS capacitors, and the C-V curves obtained from $O_2-$ and $NH_3$-annealed $HfO_2$ films are analyzed.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.715-718
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• 2003

본 논문에서는 MOSFET source/drain 고체 확산 원으로써 도핑된 폴리 실리콘을 사용하였으며 확산 후 남은 폴리 실리콘은 elevated source/drain 역할을 하여 저항을 줄여 준다. 또한 제안 된 구조는 게이트 절연막 공정 이전에 확산 공정이 이루어 지기 때문에 후속 열처리에 취약한 고유전율 게이트 절연막 공정과 금속 게이트 공정에 적합한 공정으로 적합함을 보였다.

• The Korean Journal of Ceramics
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• v.2 no.2
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• pp.111-113
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• 1996

Dielectric properties at microwave frequency region of the five-layered compound $Ba_5Nb_4O_{15}$ prepared by the conventional solid state reaction method were investigated. $Ba_5Nb_4O_{15}$ has excellent microwave dielectric characteristics; ${\varepsilon}_r$=38, Q=7500 at 10 GHz, and ${\tau}_l$=+50 ppm/K. Since this compound has a high dielectric constant, high Q and sufficiently stable characteristics, it is useful for the applications at microwave frequencies.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.1
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• pp.52-62
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• 2004

In this paper we look at the effect of Fringe-Enhanced-Barrier-lowering (FEBL) for high-K dielectric MOSFETs and the dependence of FEBL on various technological parameters (spacer dielectrics, overlap length, dielectric stack, S/D junction depth and dielectric thickness). We show that FEBL needs to be contained in order to maintain the performance advantage with scaled high-K dielectric MOSFETs. The degradation in high-K dielectric MOSFETs is also identified as due to the additional coupling between the drain-to-source that occurs through the gate insulator, when the gate dielectric constant is significantly higher than the silicon dielectric constant. The technology parameters required to minimize the coupling through the high-K dielectric are identified. It is also shown that gate dielectric stack with a low-K material as bottom layer (very thin $SiO_2$ or oxy-nitride) will be helpful in minimizing FEBL. The circuit performance issues with high-K MOS transistors are also analyzed in this paper. An optimum range of values for the dielectric constant has been identified from the delay and the energy dissipation point of view. The dependence of the optimum K for different technology generations has been discussed. Circuit models for the parasitic capacitances in high-K transistors, by incorporating the fringing effects, have been presented.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.388-388
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• 2012

In this letter, We have investigated cell characteristics of the alloy FePt-NDs charge trapping memory capacitors with high-k $Al_2O_3$ dielectrics as a blocking oxide. The capacitance versus voltage (C-V) curves obtained from a representative MOS capacitor embedded with FePt-NDs synthesized by the post deposition annealing (PDA) treatment process exhibit the window of flat-band voltage shift, which indicates the presence of charge storages in the FePt-NDs. It is shown that NDs memory with high-k $Al_2O_3$ as a blocking oxide has performance in large memory window and low leakage current when the diameter of ND is below 2 nm. Moreover, high-k $Al_2O_3$ as a blocking oxide increases the electric field across the tunnel oxide, while reducing the electric field across the blocking layer. From this result, this device can achieve lower P/E voltage and lower leakage current. As a result, a FePt-NDs device with high-k $Al_2O_3$ as a blocking oxide obtained a~7V reduction in the programming voltages with 7.8 V memory.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.140-141
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• 2007

반도체 소자의 공정에 있어서 device scaling으로 인한 고유전 게이트 산화막 (high-k dielectics thin film)의 공정 개발 확보 방안이 필요하다. 본 논문에서는 유도결합 플라즈마를 이용하여 고유전율 박막을 식각하였다. CF4, SF6 등의 가스에서 금속-F, 금속-S 결합의 낮은 휘발성으로 인하여 시료 표면에 잔류하여 낮은 식각률을 보이며 측벽 잔류물을 형성하였으며, HBr, Cl 기반 플라즈마에서 금속-Br, 금속-Cl 결합은 시료 표면으로부터 탈착이 용이하여 효과적인 식각이 이루어짐을 확인할 수 있었다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.3
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• pp.166-173
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• 2009

The reliability of hafnium oxide gate dielectrics incorporating lanthanum (La) is investigated. nMOSFETs with metal/La-doped high-k dielectric stack show lower $V_{th}$ and $I_{gate}$, which is attributed to the dipole formation at the high-k/$SiO_2$ interface. The reliability results well correlate with the dipole model. Due to lower trapping efficiency, the La-doping of the high-k gate stacks can provide better PBTI immunity, as well as lower charge trapping compared to the control HfSiO stacks. While the devices with La show better immunity to positive bias temperature instability (PBTI) under normal operating conditions, the threshold voltage shift (${\Delta}V_{th}$) at high field PBTI is significant. The results of a transconductance shift (${\Delta}G_m$) that traps are easily generated during high field stress because the La weakens atomic bonding in the interface layer.

• 전자공학회논문지 IE
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• v.43 no.4
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• pp.8-12
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• 2006

In this paper, reflectance and the dielectric characteristics for $P_2O_5$-ZnO-BaO system and $SiO_2-ZnO-B_2O_3$ system have been investigated as a function of contents of $TiO_2$. The reflectance was decreased with increasing the contents of $TiO_2$ contents, and the reflectance of $P_2O_5$-ZnO-BaO system was lowered than that of $SiO_2-ZnO-B_2O_3$ system. The dielectric constant of $P_2O_5$-ZnO-BaO system was higher than $SiO_2-ZnO-B_2O_3$ system, and the dielectric constant in the both system was increased with increasing of $TiO_2$ contents. This can explained as the space charge effects. These results are could be applied to the lower dielectrics layer of PDP required high reflective ratio and breakdown strength.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.67-70
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• 2009

Printed electronics are emerging technology to realize various microelectronic devices via a cost-effective method. Here we introduce high performance inkjet printed polymer field-effect transistors and application to complementary integrated circuits with p-type and n-type conjugated polymers. The performance of devices highly depends on the selection of dielectrics, printing condition and device architecture. The device optimization and performances of various integrated circuits, e.g., complementary inverters and ring oscillators will be mainly discussed in this talk.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.340-341
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• 2012

In this work, we investigated the effects of temperature stress on flatband voltage (VFB) shifts of HfO2-SiO2 double gate dielectrics devices. Fig. 1 shows a high frequency C-V of the device when a positive bias for 10 min and a subsequent negative bias for 10 min were applied at room temperature (300 K). Fig. 2 shows the corresponding plot when the same positive and negative biases were applied at a higher temperature (473.15 K). These measurements are based on the BTS (bias temperature stress) about mobile charge in the gate oxides. These results indicate that the positive bias stress makes no difference, whereas the negative bias stress produces a significant difference; that is, the VFB value increased from ${\Delta}0.51$ V (300 K, Fig. 1) to ${\Delta}14.45$ V (473.15 K, Fig. 2). To explain these differences, we propose a mechanism on the basis of oxygen vacancy in HfO2. It is well-known that the oxygen vacancy in the p-type MOS-Cap is located within 1 eV below the bottom of the HfO2 conduction band (Fig. 3). In addition, this oxygen vacancy can easily trap the electron. When heated at 473.15 K, the electron is excited to a higher energy level from the original level (Fig. 4). As a result, the electron has sufficient energy to readily cross over the oxide barrier. The probability of trap about oxygen vacancy becomes very higher at 473.15 K, and therefore the VFB shift value becomes considerably larger.