• 제목/요약/키워드: High-k dielectrics

검색결과 153건 처리시간 0.04초

Organosilicate Glass Dielectrics for High Performance FPD Applications

  • Choi, Dong-Kyu;Amako, Masaaki;Maghsoodi, Sina;Bilgrien, Carl
    • 한국정보디스플레이학회:학술대회논문집
    • /
    • 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.II
    • /
    • pp.832-835
    • /
    • 2005
  • Organosilicate Glass has quite a long history in the Semiconductor industry but has received very limited evaluation for Display industry applications. In this paper, we would like to introduce several kinds of Organosilicate Glasses for Display applications.

  • PDF

분광 타원계측기를 이용한 고굴절률 게이트 산화막의 광물성 분석 (Optical Properties of High-k Gate Oxides Obtained by Spectroscopic Ellipsometer)

  • 조용재;조현모;이윤우;남승훈
    • 대한기계학회:학술대회논문집
    • /
    • 대한기계학회 2003년도 추계학술대회
    • /
    • pp.1932-1938
    • /
    • 2003
  • We have applied spectroscopic ellipsometry to investigate $high-{\kappa}$ dielectric thin films and correlate their optical properties with fabrication processes, in particular, with high temperature annealing. The use of high-k dielectrics such as $HfO_{2}$, $Ta_{2}O_{5}$, $TiO_{2}$, and $ZrO_{2}$ as the replacement for $SiO_{2}$ as the gate dielectric in CMOS devices has received much attention recently due to its high dielectric constant. From the characteristics found in the pseudo-dielectric functions or the Tauc-Lorentz dispersions, the optical properties such as optical band gap, polycrystallization, and optical density will be discussed.

  • PDF

용액공정을 이용한 SiOC/SiO2 박막제조

  • 김영희;김수룡;권우택;이정현;유용현;김형순
    • 한국재료학회:학술대회논문집
    • /
    • 한국재료학회 2009년도 추계학술발표대회
    • /
    • pp.36.2-36.2
    • /
    • 2009
  • Low dielectric materials have been great attention in the semiconductor industry to develop high performance interlayer dielectrics with low k for Cu interconnect technology. In our study, the dielectric properties of SiOC /SiO2 thin film derived from polyphenylcarbosilane were investigated as a potential interlayer dielectrics for Cu interconnect technology. Polyphenylcarbosilane was synthesized from thermal rearrangement of polymethylphenylsilane around $350^{\circ}C{\sim}430^{\circ}C$. Characterization of synthesized polyphenylcarbosilane was performed with 29Si, 13C, 1H NMR, FT-IR, TG, XRD, GPC and GC analysis. From FT-IR data, the band at 1035 cm-1 is very strong and assigned to CH2 bending vibration in Si-CH2-Si group, indicating the formation of the polyphenylcarbosilane. Number average of molecular weight (Mn) of the polyphenylcarbosilane synthesized at $400^{\circ}C$ for 6hwas 2, 500 and is easily soluble in organic solvent. SiOC/SiO2 thin film was fabricated on ton-type silicon wafer by spin coating using 30wt % polyphenylcarbosilane incyclohexane. Curing of the film was performed in the air up to $400^{\circ}C$ for 2h. The thickness of the film is ranged from $1{\mu}m$ to $1.7{\mu}m$. The dielectric constant was determined from the capacitance data obtained from metal/polyphenylcarbosilane/conductive Si MIM capacitors and show a dielectric constant as low as 2.5 without added porosity. The SiOC /SiO2 thin film derived from polyphenylcarbosilane shows promising application as an interlayer dielectrics for Cu interconnect technology.

  • PDF

MOS 소자의 대체 게이트 산화막으로써 $HfO_{2}/HfSi_{x}O_{y}$ 의 구조 및 전기적 특성 분석 (Structural and electrical characterizations of $HfO_{2}/HfSi_{x}O_{y}$ as alternative gate dielectrics in MOS devices)

  • 강혁수;노용한
    • 한국전기전자재료학회:학술대회논문집
    • /
    • 한국전기전자재료학회 2001년도 하계학술대회 논문집
    • /
    • pp.45-49
    • /
    • 2001
  • We have investigated physical and electrical properties of the Hf $O_2$/HfS $i_{x}$/ $O_{y}$ thin film for alternative gate dielectrics in the metal-oxide-semiconductor device. The oxidation of Hf deposited directly on the Si substrate results in the H $f_{x}$/ $O_{y}$ interfacial layer and the high-k Hf $O_2$film simultaneously. Interestingly, the post-oxidation N2 annealing of the H102/H1Si70y thin films reduces(increases) the thickness of an amorphous HfS $i_{x}$/ $O_{y}$ layer(Hf $O_2$ layer). This phenomenon causes the increase of the effective dielectric constant, while maintaining the excellent interfacial properties. The hysteresis window in C-V curves and the midgap interface state density( $D_{itm}$) of Hf $O_2$/HfS $i_{x}$/ $O_{y}$ thin films less than 10 mV and ~3$\times$10$^{11}$ c $m^{-2}$ -eV without post-metallization annealing, respectively. The leakage current was also low (1$\times$10-s A/c $m^2$ at $V_{g}$ = +2 V). It is believed that these excellent results were obtained due to existence of the amorphous HfS $i_{x}$/ $O_{y}$ buffer layer. We also investigated the charge trapping characteristics using Fowler-Nordheim electron injection: We found that the degradation of Hf $O_2$/HfS $i_{x}$/ $O_{y}$ gate oxides is more severe when electrons were injected from the gate electrode.e electrode.e.e electrode.e.

  • PDF

Dielectric Thin Film Using Atmospheric Pressure Plasma Polymerization

  • Choi, Sung-Lan;Kim, Hong-Doo
    • 한국정보디스플레이학회:학술대회논문집
    • /
    • 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
    • /
    • pp.1444-1446
    • /
    • 2009
  • The atmospheric pressure plasma polymerization of acrylate monomers was carried out to have dielectrics with easy preparation and high performance. The effects of discharge power, monomer concentration and deposition time on film properties were investigated using various characterization tools. With proper conditions, smooth dielectric layer of 100nm thickness was obtained. Dielectric property as organic dielectric layer has been studied for future applications in organic thin film transistors(OTFT).

  • PDF

The Pulsed Id-Vg methodology and Its Application to the Electron Trapping Characterization of High-κ gate Dielectrics

  • Young, Chadwin D.;Heh, Dawei;Choi, Ri-No;Lee, Byoung-Hun;Bersuker, Gennadi
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • 제10권2호
    • /
    • pp.79-99
    • /
    • 2010
  • Pulsed current-voltage (I-V) methods are introduced to evaluate the impact of fast transient charge trapping on the performance of high-k dielectric transistors. Several pulsed I-V measurement configurations and measurement requirements are critically reviewed. Properly configured pulsed I-V measurements are shown to be capable of extracting such device characteristics as trap-free mobility, trap-induced threshold voltage shift (${\Delta}V_t$), as well as effective fast transient trap density. The results demonstrate that the pulsed I-V measurements are an essential technique for evaluating high-$\kappa$ gate dielectric devices.

펄스파워용 고전압 고에너지밀도 커패시터 개발 (Development of High Voltage and High Energy Density Capacitor for Pulsed Power Application)

  • 이병윤;정진교;이우영;박경엽;이수휘;김영광
    • 대한전기학회논문지:전기기기및에너지변환시스템부문B
    • /
    • 제52권5호
    • /
    • pp.203-210
    • /
    • 2003
  • This paper describes high voltage and high energy density capacitor developed for pulsed power applications. The rated voltage of the developed capacitor is DC 22 [kV], the capacitance is 206 [$\mu$F] and the energy density is about 0.7 [kJ/kg]. Polypropylene film and kraft paper were used as the dielectrics. The ratio of the thickness of each dielectric material which consists of the composite dielectric structure, stacking factor and the termination method were determined by the charging and discharging tests on model capacitors. In terms of energy density, the developed capacitor has higher energy density compared with the products of foreign leading companies. In addition, it has been proved that the life expectancy can be more over 2000 shots through the charging and discharging test. The voltage reversal factor was 20%. This capacitor can be used as numerous discharge applications such as military, medical, industrial fields.

웨이퍼 레벨 3D Integration을 위한 Ti/Cu CMP 공정 연구 (Ti/Cu CMP process for wafer level 3D integration)

  • 김은솔;이민재;김성동;김사라은경
    • 마이크로전자및패키징학회지
    • /
    • 제19권3호
    • /
    • pp.37-41
    • /
    • 2012
  • Cu 본딩을 이용한 웨이퍼 레벨 적층 기술은 고밀도 DRAM 이나 고성능 Logic 소자 적층 또는 이종소자 적층의 핵심 기술로 매우 중요시 되고 있다. Cu 본딩 공정을 최적화하기 위해서는 Cu chemical mechanical polishing(CMP)공정 개발이 필수적이며, 본딩층 평탄화를 위한 중요한 핵심 기술이라 하겠다. 특히 Logic 소자 응용에서는 ultra low-k 유전체와 호환성이 좋은 Ti barrier를 선호하는데, Ti barrier는 전기화학적으로 Cu CMP 슬러리에 영향을 받는 경우가 많다. 본 연구에서는 웨이퍼 레벨 Cu 본딩 기술을 위한 Ti/Cu 배선 구조의 Cu CMP 공정 기술을 연구하였다. 다마싱(damascene) 공정으로 Cu CMP 웨이퍼 시편을 제작하였고, 두 종류의 슬러리를 비교 분석 하였다. Cu 연마율(removal rate)과 슬러리에 대한 $SiO_2$와 Ti barrier의 선택비(selectivity)를 측정하였으며, 라인 폭과 금속 패턴 밀도에 대한 Cu dishing과 oxide erosion을 평가하였다.

Physical and Dielectric Properties of Aluminoborosilicate-Based Dielectrics Containing Different Divalent Oxides

  • Shin, Dong-Wook;Saji, Viswanathan S.;Gupta, Ravindra K.;Cho, Yong-Soo
    • 한국세라믹학회지
    • /
    • 제44권11호
    • /
    • pp.613-617
    • /
    • 2007
  • The variations of physical and dielectric properties of low temperature dielectrics based on typical aluminoborosilicate glasses modified with several divalent oxides were investigated. The divalent oxides studied here included CaO, MgO, BaO, SrO and ZnO. All samples containing either 35 wt% or 45 wt% alumina filler were prepared at the same processing condition and then fired at $850^{\circ}C$ for 30 min. The resultant characteristics of fired samples depended on the choice of the divalent ion and the content of the alumina filler. Except for the ZnO modification, all other samples containing 35 wt% filler demonstrated promising densification as they exhibited reasonably high densities of 3.07-3.31 $g/cm^3$ and high shrinkages of 14.0-16.4%. Particularly, the sample containing ZnO was distinguished with large variations compared to the base sample, which can be highlighted with earlier densification and crystallization at unexpectedly low temperatures. The negative effects of the ZnO modification on densification and dielectric properties were thought to be associated with earlier crystallization potentially by influencing effective densification via viscous flow. As an optimum composition, the sample containing only CaO showed the most promising characteristics such as $k{\sim}8.05$ and $tan{\delta}{\sim}0.0018$ when 35 wt% alumina filler was used.

High Performance of Printed CMOS Type Thin Film Transistor

  • You, In-Kyu;Jung, Soon-Won
    • 한국재료학회:학술대회논문집
    • /
    • 한국재료학회 2010년도 춘계학술발표대회
    • /
    • pp.17.2-17.2
    • /
    • 2010
  • Printed electronics is an emerging technology to realize various microelectronic devices via a cost-effective method. Here we demonstrated a high performance of p-channel and n-channel top-gate/bottom contact polymer field-effect transistors (FETs), and applications to elementary organic complementary inverter and ring oscillator circuits by inkjet processing. We could obtained high field-effect mobility more than $0.4\;cm^2/Vs$ for both of p-channel and n-channel FETs, and successfully measured inkjet-printed polymer inverters. The performance of devices highly depends on the selection of dielectrics, printing condition and device architecture. Optimized CMOS ring oscillators with p-type and n-type polymer transistors showed as high as 50 kHz operation frequency. This research was financially supported by development of next generation RFID technology for item level applications (2008-F052-01) funded by the ministry of knowledge economy (MKE).

  • PDF