• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.259-259
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• 2016

반도체 산업 전반에 걸쳐 이루어지고 있는 연구는 소자를 더 작게 만들면서도 구동능력은 우수한 소자를 만들어내는 것이라고 할 수 있다. 따라서 소자의 미세화와 함께 트랜지스터의 구동능력의 향상을 위한 기술개발에 대한 필요성이 점차 커지고 있으며, 고유전(high-k)재료를 트랜지스터의 게이트 절연막으로 이용하는 방법이 개발되고 있다. High-k 재료를 트랜지스터의 게이트 절연막에 적용하면 낮은 전압으로 소자를 구동할 수 있어서 소비전력이 감소하고 소자의 미세화 측면에서도 매우 유리하다. 그러나, 초미세화된 소자를 제작하기 위하여 high-k 절연막의 두께를 줄이게 되면, 전기적 용량(capacitance)은 커지지만 에너지 밴드 오프셋(band-offset)이 기존의 실리콘 산화막(SiO2)보다 작고 또한 열공정에 의해 쉽게 결정화가 이루어지기 때문에 누설전류가 발생하여 소자의 열화를 초래할 수 있다. 따라서, 최근에는 이러한 문제를 해결하기 위하여 게이트 절연막 엔지니어링을 통해서 누설전류를 줄이면서 전기적 용량을 확보할 수 있는 연구가 주목받고 있다. 본 실험에서는 high-k 물질인 Ta2O5와 SiO2를 적층시켜서 누설전류를 줄이면서 동시에 높은 캐패시턴스를 달성할 수 있는 게이트 절연막 엔지니어링에 대한 연구를 진행하였다. 먼저 n-type Si 기판을 표준 RCA 세정한 다음, RF sputter를 사용하여 두께가 Ta2O5/SiO2 = 50/0, 50/5, 50/10, 25/10, 25/5 nm인 적층구조의 게이트 절연막을 형성하였다. 다음으로 Al 게이트 전극을 150 nm의 두께로 증착한 다음, 전기적 특성 개선을 위하여 furnace N2 분위기에서 $400^{\circ}C$로 30분간 후속 열처리를 진행하여 MOS capacitor 소자를 제작하였고, I-V 및 C-V 측정을 통하여 형성된 게이트 절연막의 전기적 특성을 평가하였다. 그 결과, Ta2O5/SiO2 = 50/0, 50/5, 50/10 nm인 게이트 절연막들은 누설전류는 낮지만, 큰 용량을 얻을 수 없었다. 한편, Ta2O5/SiO2 = 25/10, 25/5 nm의 조합에서는 충분한 용량을 확보할 수 있었다. 적층된 게이트 절연막의 유전상수는 25/5 nm, 25/10 nm 각각 8.3, 7.6으로 비슷하였지만, 문턱치 전압(VTH)은 각각 -0.64 V, -0.18 V로 25/10 nm가 0 V에 보다 근접한 값을 나타내었다. 한편, 누설전류는 25/10 nm가 25/5 nm보다 약 20 nA (@5 V) 낮은 것을 확인할 수 있었으며 절연파괴전압(breakdown voltage)도 증가한 것을 확인하였다. 결론적으로 Ta2O5/SiO2 적층 절연막의 두께가 25nm/10nm에서 최적의 특성을 얻을 수 있었으며, 본 실험과 같이 게이트 절연막 엔지니어링을 통하여 효과적으로 누설전류를 줄이고 게이트 용량을 증가시킴으로써 고집적화된 소자의 제작에 유용한 기술로 기대된다.

• 한국전기전자재료학회논문지
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• 제30권7호
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• pp.432-436
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• 2017

IZO transistors with $Al_2O_3$ as gate dielectrics have been investigated. To improve permittivity in an ambient dielectric layer, we grew $Al_2O_3$ by atomic layer deposition directly onto the substrates. Then, we prepared IZO semiconductor solutions with 0.1 M indium nitrate hydrate [$In(NO_3)_3{\cdot}xH_2O$] and 0.1 M zinc acetate dehydrate [$Zn(CH_3COO)_2{\cdot}2H_2O$] as precursor solutions; the IZO solution made with a molar ratio of 7:3 was then prepared. It has been found that these oxide transistors exhibit low operating voltage, good turn-on voltage, and an average field-effect mobility of $0.90cm^2/Vs$ in ambient conditions. Studies of low-voltage driving of IZO transistors with atomic layer-deposited high-k $Al_2O_3$ as gate dielectric provide data of relevance for the potential use of these materials and this technology in transparent display devices and displays.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권2호
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• pp.169-174
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• 2014

As a versatile processing method for nanoscale memory integration, laser-induced epitaxial growth is proposed for the fabrication of vertical Si channel (VSC) transistor. The fabricated VSC transistor with 80 nm gate length and 130 nm pillar diameter exhibited field effect mobility of $300cm^2/Vs$, which guarantees "device quality". In addition, we have shown that this VSC transistor provides memory operations with a memory window of 700 mV, and moreover, the memory window further increases by employing charge trap dielectrics in our VSC transistor. Our proposed processing method and device structure would provide a promising route for the further scaling of state-of-the-art memory technology.

• 한국전기전자재료학회논문지
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• 제21권1호
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• pp.1-4
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• 2008

The electrical characteristics of polycrystalline silicon (poly-Si) thin film transistor (TFT) crystallized by excimer laser annealing (ELA) method were evaluated, The polycrystalline silicon thin-film transistor (poly-Si TFT) has higher electric field-effect-mobility and larger drivability than the amorphous silicon TFT. However, to poly-Si TFT's using conventional processes, the temperature must be very high. For this reason, an amorphous silicon film on a buried oxide was crystallized by annealing with a KrF excimer laser (248 nm)to fabricate a poly-Si film at low temperature. Then, High permittivity $HfO_2$ of 20 nm as the gate-insulator was deposited by atomic layer deposition (ALD) to low temperature process. In addition, the solid phase crystallization (SPC) was compared to the ELA method as a crystallization technique of amorphous-silicon film. As a result, the crystallinity and surface roughness of poly-Si crystallized by ELA method was superior to the SPC method. Also, we obtained excellent device characteristics from the Poly-Si TFT fabricated by the ELA crystallization method.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.411.1-411.1
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• 2016

In this study, we examined the effects of boron doping on the dielectric reliability of solution processed aluminum oxide ($Al_2O_3$). When boron is doped in aluminum oxide, the hysteresis reliability is improved from 0.5 to 0.4 V in comparison with the undoped aluminum oxide. And the accumulation capacitance is increased when boron was doped, which implying the reduction of the thickness of dielectric film. The improved dielectric reliability of boron-doped aluminum oxide is originated from the small ionic radius of boron ion and the stronger bonding strength between boron and oxygen ions than that of between aluminum and oxygen ions. Strong boron-oxygen ion bonding in aluminum oxide results dielectric film denser and thinner. The leakage current of aluminum oxide also reduced when boron was doped in aluminum oxide.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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• pp.995-997
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• 2009

$In_2O_3$ thin-film transistors (TFTs) were fabricated on various dielectrics [$SiO_2$ and self-assembled nanodielectrics (SANDs)] by spin-coating a $In_2O_3$ film precursor solution consisting of methoxyethanol (solvent), ethanolamine (EAA, base), and $InCl_3$ as the $In^{3+}$ source. Importantly, an optimized film microstructure characterized by the high-mobility $In_2O_3$ 004 phase, is obtained only within a well-defined base: $In^{3+}$ molar ratio. The greatest electron mobilities of ~ 44 $cm^2$, for EAA:$In^{3+}$ molar ratio = 10, $V^{-1}s^{-1}$, is measured for $n^+$-Si/SAND/$In_2O_3$/Au devices. This result combined with the high $I_{on}:I_{off}$ ratios of ~ $10^6$ and very low operating voltages (< 5 V) is encouraging for high-speed applications.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2002년도 International Meeting on Information Display
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• pp.184-187
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• 2002

In this work, the electrical characteristics of organic thin film transistors with the stacked organic gate insulators have been studied. PVP(Polyvinylphenol) and polystyrene were used as gate insulating materials. Both the high dielectric constant of PVP and better insulating capability of polystyrene were compensatorily adopted in two different stacking orders of PVP-polystyrene and polystyrene-PVP. The output characteristics of the device with the stacked gate insulator showed substantial improvement compared with those of the devices with either PVP or polystyrene gate insulator: Furthermore, these stacked organic gate insulators can differently affect the TFT characteristics with the stacking orders. The electrical properties of TFTs with organic gate insulators stacked in different orders are discussed.

• 한국응용과학기술학회지
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• 제29권2호
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• pp.184-192
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• 2012

본 논문은 절연유 불포함 재활용 가능 전력케이블 절연체에 동일배열 폴리프로필렌(IPP) 기반 열가소성 폴리올레핀 엘라스토머(TPO) 나노복합체 사용 가능성을 문헌적으로 고찰한 리뷰논문이다. 2010년 IPP 기반 나노복합 유전체는 파워 커패시터 연구에서 유전손실을 제외한 고전압 특성이 크게 향상되었다. IPP 기반 TPO 나노복합체 사용 자동차 외장부품 연구에서는 나노충전제 최대 3 wt% 함유로 전력케이블 절연체의 필수특성인 저온 충격성을 비롯한 기계적 특성향상이 보고 되었다. 특히 유전손실의 원천인 상용화제 사용의 최소화 기술이 보고되어, 3 wt% 이하 나노충전제 함유 IPP 기반 TPO의 전기적 특성조사가 필요하다.

• 한국재료학회지
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• 제29권8호
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• pp.463-468
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• 2019

The electrical and interfacial properties of $HfO_2/Al_2O_3$ and $Al_2O_3/HfO_2$ dielectrics on AlN/p-Ge interface prepared by thermal atomic layer deposition are investigated by capacitance-voltage(C-V) and current-voltage(I-V) measurements. In the C-V measurements, humps related to mid-gap states are observed when the ac frequency is below 100 kHz, revealing lower mid-gap states for the $HfO_2/Al_2O_3$ sample. Higher frequency dispersion in the inversion region is observed for the $Al_2O_3/HfO_2$ sample, indicating the presence of slow interface states A higher interface trap density calculated from the high-low frequency method is observed for the $Al_2O_3/HfO_2$ sample. The parallel conductance method, applied to the accumulation region, shows border traps at 0.3~0.32 eV for the $Al_2O_3/HfO_2$ sample, which are not observed for the $Al_2O_3/HfO_2$ sample. I-V measurements show a reduction of leakage current of about three orders of magnitude for the $HfO_2/Al_2O_3$ sample. Using the Fowler-Nordheim emission, the barrier height is calculated and found to be about 1.08 eV for the $HfO_2/Al_2O_3$ sample. Based on these results, it is suggested that $HfO_2/Al_2O_3$ is a better dielectric stack than $Al_2O_3/HfO_2$ on AlN/p-Ge interface.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.477-477
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• 2008

For more than three decades, the gate dielectrics in CMOS devices are $SiO_2$ because of its blocking properties of current in insulated gate FET channels. As the dimensions of feature size have been scaled down (width and the thickness is reduced down to 50 urn and 2 urn or less), gate leakage current is increased and reliability of $SiO_2$ is reduced. Many metal oxides such as $TiO_2$, $Ta_2O_4$, $SrTiO_3$, $Al_2O_3$, $HfO_2$ and $ZrO_2$ have been challenged for memory devices. These materials posses relatively high dielectric constant, but $HfO_2$ and $Al_2O_3$ did not provide sufficient advantages over $SiO_2$ or $Si_3N_4$ because of reaction with Si substrate. Recently, $HfO_2$ have been attracted attention because Hf forms the most stable oxide with the highest heat of formation. In addition, Hf can reduce the native oxide layer by creating $HfO_2$. However, new gate oxide candidates must satisfy a standard CMOS process. In order to fabricate high density memories with small feature size, the plasma etch process should be developed by well understanding and optimizing plasma behaviors. Therefore, it is necessary that the etch behavior of $HfO_2$ and plasma parameters are systematically investigated as functions of process parameters including gas mixing ratio, rf power, pressure and temperature to determine the mechanism of plasma induced damage. However, there is few studies on the the etch mechanism and the surface reactions in $BCl_3$ based plasma to etch $HfO_2$ thin films. In this work, the samples of $HfO_2$ were prepared on Si wafer with using atomic layer deposition. In our previous work, the maximum etch rate of $BCl_3$/Ar were obtained 20% $BCl_3$/ 80% Ar. Over 20% $BCl_3$ addition, the etch rate of $HfO_2$ decreased. The etching rate of $HfO_2$ and selectivity of $HfO_2$ to Si were investigated with using in inductively coupled plasma etching system (ICP) and $BCl_3/Cl_2$/Ar plasma. The change of volume densities of radical and atoms were monitored with using optical emission spectroscopy analysis (OES). The variations of components of etched surfaces for $HfO_2$ was investigated with using x-ray photo electron spectroscopy (XPS). In order to investigate the accumulation of etch by products during etch process, the exposed surface of $HfO_2$ in $BCl_3/Cl_2$/Ar plasma was compared with surface of as-doped $HfO_2$ and all the surfaces of samples were examined with field emission scanning electron microscopy and atomic force microscope (AFM).