• Proceedings of the KSR Conference
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• 2008.11b
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• pp.1988-1998
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• 2008

Performed was a survey to find the level of interest on passenger services using IT and smart sensor technology in connection with High Speed Train development in Korea. The survey respondents were sampled from the KTX passengers, KTX crews, Korail employees, IT or sensor experts, and rolling stock experts. The results of the survey were categorized as importance, urgency/necessity, importance vs urgency/necessity, improvement measure, preferable activities based on the trip length, and inconveniencies. By analyzing the results, service items that can be implemented to the High Speed Train were recognized. The results showed that a passenger tends to expect to have his/her comfort and convenience, an attendant safety and serviceability, a Korail employee information provision and serviceability, an IT/sensor expert technological implementation done, and a rolling stock expert implementation done in practical level.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.48 no.8
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• pp.426-430
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• 1999

In this paper, a speed sensorless algorithm for a high-speed induction motor is proposed. The proposed algorithm simply estimates rotor speed by integrating the deviation between the command current value of a controller and the real current value of the motor. To estimate rotor speed without a speed sensor, a fuzzy speed controller and a neural network speed estimator are applied. Computer simulation and implementation of the proposed system is described.

• Journal of Korea Society of Industrial Information Systems
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• v.19 no.3
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• pp.1-7
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• 2014

This paper describes the implementation of high speed comparator for the ATE (automatic test equipment) system. The comparator block is composed of continuous comparator, differential difference amplifier(DDA) and output stage. For the wide input dynamic range of 0V to 5V, and for the high speed operation (1~800MHz), high speed rail-to-rail amplifier is used in the first stage. And hysteresis circuits, pre-amp and latch are followed for high speed operation. To measure the difference of output signals between the two devices under test (DUTs), a DDA is applied because it can detect the differences of both common signals and differential signals. This comparator chip was implemented with $0.18{\mu}m$ BCDMOS process and can compare the signal difference of 5mV up to the frequency range of 800 MHz. The chip area of the comparator is $620{\mu}m{\times}830{\mu}m$.

• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.275-278
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• 2000

As the operating frequency of digital modules in network system becomes fast, integrity of signals between modules is regarded as a important factor in high speed system design. To guarantee the signal integrity, many factors that deteriorate quality of signal should be considered. In this paper, we survey many factors which be considered while in designing and imp]ementing the backplane for high speed router and analyze the simulation result and experimental result.

• Proceedings of the IEEK Conference
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• 2003.07c
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• pp.2637-2640
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• 2003

In this paper, we propose a simple and efficient data input/output block with high speed between Motorola MPC8XX microprocessor and memory devices. Proposed method is capable of high speed data read and write using the address decoder and the burst cycle between Motorola PowerPC based MPC8XX microprocessor and fixed address locating memory devices such as FIFO, PCMCIA card, and so on. Experimental results are given our findings and discussions.

• Proceedings of the KIEE Conference
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• 1997.11a
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• pp.623-625
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• 1997

This paper deals with the simulator for the diagnosis systems of high speed train. The purpose of this simulator is the verification of diagnosis systems. In this paper, the configuration of high speed train is investigated and the implementation model of power car is proposed. According to the model, mathematical equation is constructed. Dynamic simulation is executed and analyzed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.11B
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• pp.1020-1029
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• 2008

This paper proposes an high speed pattern matching algorithm and its implementation. The pattern matcher is used to check patterns from realtime input packet. The proposed algorithm can find exact string, range of string values, and combination of string values from input packet at high speed. Given string and rule set are modelled as a state transition graph which can find overlapped strings simultaneously, and the state transition graph is partitioned according to input implicants to reduce implementation complexity. The pattern matcher scheme uses the transformed state transition graph and input packet as an input. The pattern matcher was modelled and implemented in VHDL language. Experimental results show the proprieties of the proposed approach.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.948-949
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• 2008

In this paper, an effect on power conversion unit in next generation high-speed train by loss of contact between a contact wire and pantograph supplied electrical power to high-speed train are investigated. One of the most important needs accompanied by increasing the speed of high-speed train is reduced that arc phenomenon by loss of contact brings out EMI. To analysis of conducted EMI source on powering mode of next generation high-speed train, it is necessary electrical modeling system between the contact wire and the pantograph according with loss of contact. Therefore analytical model of a contact wire and a pantograph is constructed to simulate the behaviour of loss of contact. The reliability of the modeling system is verified by simulation implementation on loss of contact.

• Journal of electromagnetic engineering and science
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• v.6 no.3
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• pp.147-154
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• 2006

In this paper, we propose and present implementation results of a high-speed turbo decoding algorithm. The latency caused by (de) interleaving and iterative decoding in a conventional maximum a posteriori(MAP) turbo decoder can be dramatically reduced with the proposed design. The source of the latency reduction is come from the combination of the radix-4, dual-path processing, parallel decoding, and rearly-stop algorithms. This reduced latency enables the use of the turbo decoder as a forward error correction scheme in real-time wireless communication services. The proposed scheme results in a slight degradation in bit-error rate(BER) performance for large block sizes because the effective interleaver size in a radix-4 implementation is reduced to half, relative to the conventional method. Fixed on the parameters of N=212, iteration=3, 8-states, 3 iterations, and QPSK modulation scheme, we designed the adaptive high-speed turbo decoder using the Xilinx chip (VIRTEX2P (XC2VP30-5FG676)) with the speed of 17.78 Mb/s. From the results, we confirmed that the decoding speed of the proposed decoder is faster than conventional algorithms by 8 times.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.8C
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• pp.801-805
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• 2009

The importance of high-speed networking is ever increasing to better support multimedia application such as video conferencing. It is crucial to synchronize the network so that the delay between computers on the network is minimized. In high-speed LAN, for example, most computers use clocks with almost same frequency to minimize the delay for data transmission. However, because of the deviation of transmitter's and receiver's clock frequency and phase difference there can be a metastability problem. Elasticity buffer is to provide a solution for this situation and this paper presents an implementation is a high-speed elasticity buffer.