• 전자공학회논문지 IE
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• v.44 no.3
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• pp.12-22
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• 2007

In this paper, we designed of the high speed digital neuron processor in order to digital neural networks. we designed of the MAC(Multiplier and Accumulator) operation unit used residue number system without carry propagation for the high speed operation. and we implemented sigmoid active function which make it difficult to design neuron processor. The Designed circuits are descripted by VHDL and synthesized by Compass tools. we designed of MAC operation unit and sigmoid processing unit are proved that it could run time 19.6 nsec on the simulation and decreased to hardware size about 50%, each order. Designed digital neuron processor can be implementation in parallel distributed processing system with desired real time processing, In this paper.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.35 no.6
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• pp.556-563
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• 2007

The current trend of low cost ultra-small satellites is to utilize Commercial Off the Shelf (COTS) parts to save cost, and accordingly, Command and Data Handling (C&DH) that operates the satellite and collects/processes the data is also designed and developed around commercial controllers. However, functionalities of commercial controllers are limited according to the specs outlined by the manufacturer. In order for the commercial controllers to be used for satellites where variety of interfaces is required, a separate interface circuit is required. Therefore, a Multi Digital Data Control System (MDDCS) using Field Programmable Gate Array (FPGA) has been developed in order to expand multiple digital interfaces that are not supported by the commercial controller, and also to compensate for SEU. This has been implemented on Actel A3P1000 using Very High Speed Integrated Circuits Hardware Description Language (VHDL).

• The Transactions of the Korean Institute of Power Electronics
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• v.10 no.3
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• pp.290-295
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• 2005

The incremental encoder has been mostly used to measure the speed and position of the motor. As the output signals of encoder are high frequency digital signals, they have much influence on radiation noises due to switching of the power semiconductor circuits. It is so difficult to suppress the noises with the conventional LPF. In this paper, the hardware digital filter for suppressing noises in the output signals of the encoder signals is developed. As both the clock frequency and counter in the digital filter for encoder are easily adjusted according to the kinds of noises, any noises in the encoder can be entirely eliminated. The performance of the digital filter has been verified by simulation and experimental results.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1996.11a
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• pp.353-356
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• 1996

Ultra-high-speed analog and digital ICs (integrated circuits) fur 10Gbit/sec optical communication systems have been designed, fabricated and analyzed in this research. These circuits, which are laser diode (LD) driver, pre-amplifier, automatic gain controlled (AGC) amplifier, limiting amplifier and decision circuit, have been implemented with AIGaAs/GaAs heterojunction bipolar transistors (HBTs). The optimized AIGaAs/GaAs HBTs for the 10Gbps circuits in this work showed the cutoff and maximum oscillation frequencies of 65㎓ and 53㎓, respectively. It is demonstrated in this paper that the 10Gbps optical communication system can be realized with the ICs designed and fabricated using AlGaAs/GaAs HBTs.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.8
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• pp.1-7
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• 1998

This paper reports a dispersion compensation technique to implement tje distortionless transmission line by satisfying the heaviside conditon. Because of the skin depth for aconductor, compensation condition is dependent on the freuqncy variation. For this reason, first, the resistance have been chaacterized in awide range of frequencies, and then found the effective conductivity of the substrate which satisfied the heaviside condition. The phase velocity and the characteristics impedance are prresented nearly constant over a wideband frequency range.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.277-280
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• 2001

The proposed clock generator lowers the operating frequency in a system core though it keeps data bandwidth high because it has a multiphase clocking architecture. Moreover. it has a dual loop which is comprised of an inner analog phase generation loop and outer digital phase control loop. It has both advantages of DLL's wide operating range and DLL's low jitter The proposed design has been demonstrated in terms of the concept and Hspice simulation. All circuits were designed using a 0.25${\mu}{\textrm}{m}$ CMOS process and simulated with 2.5 V power supply.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.579-584
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• 2008

A novel nondestructive testing (NDT) system, which is able to detect a crack with high speed and high spatial resolution, is urgently required for inspecting small cracks on express train wheels. This paper proposes an improved signal processing circuits, which uses the multiple amplifying circuits and the crack indicating pulse output system of the previous scan-type magnetic camera. Hall sensors are arrayed linearly, and the wheel is rotated with static speed in the vertical direction to sensor array direction. Each Hall voltages are amplified, converted and immediately operated by using, amplifying circuits, analog-to-digital converters and $\mu$-processor, respectively. The operated results, ${\partial}V_H/{\partial}t$, are compared with a standard value, which indicates a crack existence. If the ${\partial}V_H/{\partial}t$ is larger than standard value, the pulse signal is output, and indicates the existence of crack. The effectiveness of the novel method was verified by examine using cracks on the wheel specimen model.

• Journal of Sensor Science and Technology
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• v.26 no.3
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• pp.209-213
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• 2017

The delay-insensitive Null Convention Logic (NCL) asynchronous design as one of innovative asynchronous logic design methodologies has many advantages of inherent robustness, power consumption, and easy design reuses. However, transistor-level structures of conventional NCL gate cells have weakness of high area overhead and high power consumption. This paper proposes a new NCL gate based on power gating structure. The proposed $4{\times}4$ NCL multiplier based on power gating structure is compared to the conventional NCL $4{\times}4$ multiplier and MTNCL(Multi-Threshold NCL) $4{\times}4$ multiplier in terms of speed, power consumption, energy and size using PTM 45 nm technology.

• IEMEK Journal of Embedded Systems and Applications
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• v.9 no.3
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• pp.173-182
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• 2014

The CRT monitor display system for SONAR signal that are commonly used in ships or naval vessels uses vector scanning method. Therefore the processing circuits of the system are complex. Also the purchase of parts is difficult as well as high-cost because the production had been shut down. FPGA-based embedded system is flexible to various digital applications because it can be able to simplify processing circuits and to make a easy customized design for end user, and it provides low-cost high-speed performance. In this paper, we describe an implementation of FPGA embedded system for real-time SONAR signal display using the triple buffering method to overcome some weakness of existing CRT system. Our system provides real-time acquisition and display capability of SONAR signal, and removes afterimage effect that is a critical problem of the system proposed in the preceding study.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.12 no.4
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• pp.347-356
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• 1987

This paper is to propose a new line code suitable for a high speed unipolar pulse transmission system, such as a high speed optical digital transmission system. The original information speed can be converted into the transmission speed $\frac{(m+1)}{m}$ by the speed converter. Then this code, named mBiZ code, is generated by means of an Exclusive NOR between the bit stream inserted a space into every m bits and the bit stream delayed by the time slot allocated a single bit at the output coded sequence. Therefore, a mBiZ code can reduce a redundancy in the line code for transmission and its conversion circuits can be devised easily. The mBiZ code can also suppress undesirable long consecuitive identical digits and make line code balance in the mark and space ratio. Therefore, high frequency and low frequency components in power spectrum of a mBiZ code can be suppessed.