• Proceedings of the Korea Contents Association Conference
• /
• 2004.05a
• /
• pp.372-376
• /
• 2004

Digital memory circuits have been developed very fast according to the progress of semiconductor technology But It was very difficult to memorize a high frequency radio signal. Many years ago an analog loop was used for store of radio frequency signal, and the digital radio frequency memory was made to the development of wideband amplifier and high speed sampler. We present a design of wide-band DRFM using Johnson code and the simulation results with respect to the sampling speed. in this paper.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.18 no.2 s.117
• /
• pp.199-205
• /
• 2007

In this paper, a novel hexagonal-shaped electromagnetic bandgap(EBG) power plane for the suppression of the ground bounce noise(GBN) in high-speed circuits is proposed. The proposed structure consists of hexagonal-shaped unit cells and detoured bridges connecting the unit cells. The hexagonal-shaped unit cells could omni-directionally suppress the GBN in digital circuits. The fabricated power plane's omni-directional -30 dB suppression bandwidth is from 330 MHz to 5.6 GHz. Then the proposed structure suppresses electromagnetic interference(EMI) caused by the GBN within the stopband. As a result, the proposed structure is expected to be conducive solving EMI problem in high-speed circuits.

• Journal of the Institute of Convergence Signal Processing
• /
• v.9 no.3
• /
• pp.224-229
• /
• 2008

In the paper, a new Constraint algorithm is proposed to solve the fan-in problem occurred in the encoding circuitry of an ADC. The Flash ADC architecture uses a Double-Base Number System(DBNS). The DBNS has been known to represent the Multidimensional Logarithmic Number System (MDLNS) used for implementing the multiplier accumulator architecture of FIR filter in Digital Signal Processing (DSP) applications. The authors use the DBNS with the base 2 and 3 in designing ADC encoder circuits, which is called as Double Base Integer Encoder(DBIE). A symmetric map is analyzed first, and then asymmetric map is followed to provide addition ready DBNS for DSP circuitry. The simulation results of the DBIE circuits in 6-bit and 8-bit ADC show the effectiveness of the Constraint algorithm with $0.18{\mu}m$ CMOS technology. The DBIE yields faster processing speed compared to the speed of Fat Tree Encoder (FAT) circuits by 17% at more power consumption by 39%.

• Proceedings of the IEEK Conference
• /
• 2001.06b
• /
• pp.253-256
• /
• 2001

This paper introduces the design of high-speed analog- to-digital converter for high-definition TV, camcorders, portable equipments and implemented in a 0.65${\mu}{\textrm}{m}$ CMOS technology. Key circuits developed for low power and high speed A/D converter are a dynamic comparator that consumes no static power, a source follower buffered op amp that achives wide bandwidth using large input devices. The converter achieves low power dissipation of 40-mW at 3.3-V power supply. Measured performance includes 0.53 LSB of INL and 0.48 LSB of DNL while sampling at 60MHz.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.6 no.5
• /
• pp.401-406
• /
• 2005

Digital memory circuits have been developed very fast according to the progress of semiconductor technology. But it was very difficult to memorize a wideband radio frequency signals. Many years ago, an analog frequency memory loop(FML) was used for store of radio frequency signal and the digital radio frequency memory was made according to the development of wideband amplifier and high speed sampler. We present a design of wideband digital radio frequency reproduction device using ladder circuit and the simulation results with respect to the sampling speed in this paper.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.42 no.12
• /
• pp.159-164
• /
• 2005

Recently, it has demanded high-speed digital circuits as information increase. Therefore, electromagnetic characteristics of compact microwave circuit occurred importantly. And, the effect of the imperfect ground plane on the signal integrity and influence of coupling between two parallel lines for high-speed digital transmission line on the printed circuit board is investigated by FDTD simulations in 3-D electromagnetic analysis method. The results of FDTD simulation are compared with the ADS simulation in commercial software, analyzed lumped element of modeling and electromagnetic wave's radiation of slot as frequency. As a consequence, when the slot in the ground plane is under microstrip line, it has much effect on propagation of wave.

• Journal of information and communication convergence engineering
• /
• v.1 no.4
• /
• pp.177-182
• /
• 2003

Conventional multilayer feedforward artificial neural networks are very effective in dealing with spatial problems. To deal with problems with time dependency, some kinds of memory have to be built in the processing algorithm. In this paper we show how the newly proposed Serial Input Neuron (SIN) convolutional decoders can be derived. As an example, we derive the SIN decoder for rate code with constraint length 3. The SIN is tested in Gaussian channel and the results are compared to the results of the optimal Viterbi decoder. A SIN approach to decode convolutional codes is presented. No supervision is required. The decoder lends itself to pleasing implementations in hardware and processing codes with high speed in a time. However, the speed of the current circuits may set limits to the codes used. With increasing speeds of the circuits in the future, the proposed technique may become a tempting choice for decoding convolutional coding with long constraint lengths.

• ETRI Journal
• /
• v.37 no.6
• /
• pp.1154-1164
• /
• 2015

This paper proposes a fully sensorless driver for a permanent magnet synchronous motor (PMSM) integrated with a digital motor controller and an analog pre-driver, including sensing circuits and estimators. In the motor controller, a position estimator estimates the back electromotive force and rotor position using a sliding-mode observer. In the pre-driver, drivers for the power devices are designed with a level shifter and isolation technique. In addition, a current sensing circuit measures a three-phase current. All of these circuits are integrated in a single chip such that the driver achieves control of the speed with high accuracy. Using an IC fabricated using a $0.18{\mu}m$ BCDMOS process, the performance was verified experimentally. The driver showed stable operation in spite of the variation in speed and load, a similar efficiency near 1% compared to a commercial driver, a low speed error of about 0.1%, and therefore good performance for the PMSM drive.

• Journal of the Korean Institute of Telematics and Electronics D
• /
• v.35D no.7
• /
• pp.63-71
• /
• 1998

Generally, electronic packaging designer uses HSPICE SOFTWARE TOOL to validate electric characteristics of traces layout before layout traces in PCB in hundreds Mb/s high speed digital circuits. We are in need of a plated through hole (PTH) model and a connector model to use HSPICE SOFTWARE TOOL. Those models have not been perfectly defined for HSPICE simulation. In this paper, we define a PTH model and a connector model for HSPICE simulation and discuss application range for these models. Th emodels are analytic models very applicable for HSPICE simulation and are used to analyze electric characteristic of the PTH and the connector in thetraces layout in high speed digital circuit.

• International Journal of Precision Engineering and Manufacturing
• /
• v.2 no.4
• /
• pp.81-88
• /
• 2001

We present a new digital phase measuring method for heterodyne optical interferometry, which providers high measuring speed up to 6 m/s with a fine displacement resolution of 0.1 nanometer. The key idea is combining two distinctive digital phase measuring techniques with mutually complementary characteristics to earth other one is counting the Doppler shift frequency counting with 20 MHz beat frequency for high-velocity measurement and the other is the synchronous phase demodulation with 2.0 kHz beat frequency for extremely fine displacement resolution. The two techniques are operated in switching mode in accordance wish the object speed in a synchronized way. Experimental results prove that the proposed dual mode phase measuring scheme is realized with a set of relatively simple electronic circuits of beat frequency shifting, heterodyne phase detection. and low-pass filtering.