• 한국정보디스플레이학회:학술대회논문집
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• 2003.07a
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• pp.105-108
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• 2003

A new high speed addressing method is proposed to reduce the addressing time below lus per line in AC PDP. In this method, the priming discharge is used to achieve a high speed addressing without adding an auxiliary electrode. Two different types of priming discharges were studied to achieve a high speed addressing and also reduce the inherent light output caused by the priming discharge in order to improve the contrast ratio characteristics. In the panel experiment, the addressing was successfully done with a lus address pulse width in the new method and the better contrast ratio was achieved in the Y-A priming rather than the Y-X priming case even though the reduction of the address period was smaller than that of the Y-X priming due to the extra address time for the priming discharges.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1181-1184
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• 2007

The new self-priming addressing driving scheme was proposed to improve an address discharge time lag. It utilizes the priming effect maintaining the priming ramp discharge during an address period and the address discharge time lag is significantly improved. In this study, the basic characteristics of the priming ramp discharge are presented.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.54 no.6
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• pp.269-273
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• 2005

In order to achieve high efficiency and low cost, new high-speed addressing method is suggested. This can be implemented by reducing the address discharge time lag through the priming effect. This paper suggests a new ADR(Address During Reset) driving method which provides priming particles by a separated driving method without adding auxiliary electrode or auxiliary discharge. The experimental results show an approximately 100ns reduction in the formative delay time of address discharge and a reduction in jitter of over 200ns. Also, due to enough time being available for reset, there was a reduction of about 29$\%$ in linht emitted during the reset period considerably.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.115-118
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• 2007

Luminous efficacy of 6.0 lm/W has been realized by introducing a spatial positive column discharge together with delayed D pulses, shared sustain pulse voltage, and low sustain frequency drive. Also a high speed addressing of $0.25{\mu}s$ was achieved. The luminance was $157cd/m^2$, which is high enough for a 260-in. FHD display.

• Journal of Ubiquitous Convergence Technology
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• v.1 no.1
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• pp.42-46
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• 2007

In this paper, we proposed an efficient short address allocation mechanism for WiBEEM devices using NAA(Next Address Available) algorithm. The proposed addressing mechanism is based upon the NAA information that is delivered over the beacons every time it is transmitted at the beginning of each super-frame. The NAA-based addressing mechanism is not a systematic way of allocating short addresses to newly joining devices and thus tree-routing cannot be supported. However, it has great advantages when U-City core services including U-Parking Lot System or ATIS(Advanced Traveler Information System) services that require high-speed mobility are considered. Moreover, the proposed addressing mechanism can provide significant expandability of the wireless network to various applications and fast device discovery.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.23 no.2
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• pp.45-52
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• 2009

This study is related to the realization of high speed address driving method for Full-HD PDP. The new self-priming addressing(SPA) driving scheme was proposed to improve an address discharge time lag, which utilizes the priming effect maintaining the priming discharge during an address period. In this study, the basic characteristics of the priming ramp discharge were investigated and optimize the reset pulse and priming pulse. It is noted that the address discharge time lag is significantly improved from 1.2[${\mu}s$] to 0.8[${\mu}s$] when the slope of the priming ramp pulse is below 0.1[$V/{\mu}s$].

• Proceedings of the KIPE Conference
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• 2007.11a
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• pp.215-217
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• 2007

Recently, the demand for high definition TV is being increased by beginning of the digital broadcasting. The higher resolution of PDP is, the longer addressing time become, then, the sustain period for display image decreases. Because of the reason, dual-scan method which synchronously write information of an image on top and bottom of the screen is used for the high definition PDP. However, as the price competition of PDP becomes severe, we can`t avoid turning to a single-scan method which uses only a half of an expensive address IC. Accordingly, the sustain period becomes much shorter than prior method. In case of XGA level, it is impossible to display, eventually. In this paper, we are going to prove usefulness by realizing negative reset waveform and the driving circuit for high speed addressing.

• Proceedings of the Optical Society of Korea Conference
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• 1999.08a
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• pp.204-205
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• 1999

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07a
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• pp.647-650
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• 2005

A new driving scheme, Address and Display Period Complex Driving for Expanding Gray Scale(ACE), is proposed by mixing Address Display period Separated(ADS) and Address While Display(AWD). In this method scan lines are divided in blocks driving by AWD and scan lines in block progress sequential high speed addressing. ADS driving get accomplished in low gray level for expanding gray scale. Scan time is reduced and the number of subfields is increased by high speed addressing of ACE. That expands the gray scale and decreases the dynamic false contour. Also, that improves contrast by using ramp reset.

• KIEE International Transactions on Electrophysics and Applications
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• v.5C no.5
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• pp.183-190
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• 2005

In order to drive the high-density plasma displays, a high-speed driving technology must be researched. In this experiment, the relationship between the width of the address electrode and high-speed driving is analyzed using the Vt close curve and the panel structure for high-speed driving is proposed. In addition we show that the wider the width of the address electrode is, the narrower the width of the scan pulse becomes. Therefore, we could achieve the minimum data voltage of 50.1V at a scan pulse width of $1.0/{\mu}s$ and a ramp voltage of 210V at an address electrode width of $180/{\mu}m$ for the high-speed driving 4-inch test PDP.