• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.280-285
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• 2015

A fully integrated high-efficiency linear CMOS power amplifier (PA) is developed for 802.11n WLAN applications using the 65-nm standard CMOS technology. The transformer topology is investigated to obtain a high-efficiency and high-linearity performance. By adopting a 2:2 output transformer, an optimum impedance is provided to the PA core. Besides, a LC harmonic control block is added to reduce the AM-to-AM/AM-to-PM distortions. The CMOS PA produces a saturated power of 26.1 dBm with a peak power-added efficiency (PAE) of 38.2%. The PA is tested using an 802.11n signal, and it satisfies the stringent error vector magnitude (EVM) and mask requirements. It achieves -28-dB EVM at an output power of 18.6 dBm with a PAE of 14.7%.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.7
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• pp.807-815
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• 2019

In this paper, we design a power amplifier to support quad-band in wireless communication devices using RF CMOS 180-nm process. The proposed power amplifier consists of low-band 0.9, 1.8, and 2.4 GHz and high-band 5 GHz. We proposed a structure that can support each input matching network without using a switch. For maximum linear output power, the output matching network was designed for impedance conversion to the power matching point. The fabricated quad-band power amplifier was verified using modulation signals. The long-term evolution(LTE) 10 MHz modulated signal was used for 0.9 and 1.8 GHz, and the measured output power is 23.55 and 24.23 dBm, respectively. The LTE 20 MHz modulated signal was used for 1.8 GHz, and the measured output power is 22.24 dBm. The wireless local area network(WLAN) 802.11n modulated signal was used for 2.4 GHz and 5.0 GHz. We obtain maximum linear output power of 20.58 dBm at 2.4 GHz and 17.7 dBm at 5.0 GHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.2
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• pp.174-180
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• 2008

The pulsed amplifier which switches the main supply voltage of RF amplifier according to input pulse signal has good efficiency and low noise level between pulses. And it has simple structure because it doesn't need a pulse modulator at input port. The pulsed amplifier using the conventional switching circuit has slow fall time compared to rise time. We proposed the novel switching circuit for improving the fall time of pulsed amplifier The proposed switching circuit is implemented by replacing FET of conventional circuit with BJT. As a result of appling this circuit to RF pulsed amplifier, the rise and fall time are 5.7 ns and 21.9 ns at 27 dBm output power, respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.9
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• pp.1065-1071
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• 2010

In this paper, we proposed a novel harmonic load circuit to design a high efficiency class-F amplifier. The proposed load circuit controls termination impedances to enhance the efficiency of class-F power amplifier. The termination impedances at the 2nd and the 3rd harmonics are showed short and open condition, respectively. Also, a fabricated load circuit showed an attenuation characteristic more than 29 dB, that is enough to eliminate harmonics of the class-F power amplifier. The measured drain and power-added efficiency are 75.7 % and 71.3 % at the point of maximum output power 35.17 dBm.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2003.09b
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• pp.118-121
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• 2003

Generally, the repeater in CDMA(Code Division Multiple Access) included HPA(HI-Power Amplifier) to amplifier communication signals. Also , HPA contained PD(Predistortor) to maintain the linearization of amplifier characteristics. A configuration component of PD have been used electricity nonlinear devices such that diode. But this diode takes many influences at the circumstance temperature. Consequently, it can't maintain output linearization, and drop the communication quality. The manufacturer set bias of the circuit to the manual at the first out of ware-house low But the Q-point changes according to the change of the high temperature or low temperature. Therefore, we designed a system to maintain the Q-point by FDM(Fuzzy Decision Maker) in this paper.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.8
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• pp.795-801
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• 2014

This paper presents an efficiency enhancement for the high power amplifier using DDBS(Digitally-controlled Dynamic Bias Switching) method which dynamically provides the power amplifier with two bias voltage levels according to the input envelope signal. It is quite easy to adjust the control signal by using a digital processing. The fabricated DDBS PA was evaluated using an 64 QAM FDD LTE signal, which has a center frequency of 2.6 GHz, a bandwidth of 10 MHz and a PAPR of 9.5 dB. The DDBS increases the power amplifier's PAE(Power-Added Efficiency) from 40.9 % to 48 %, at an average output power level of 43 dBm.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.3
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• pp.276-282
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• 2015

Until recently, power amplifiers using LDMOS were Class-AB and Doherty type, and showed 55 % efficiency for narrowband of 60 MHz bandwidth. However, owing to the RRH application of base stations power amplifier module, a bandwidth expansion of at least 100 MHz and high efficiency power amplifiers of at least 60 % power efficiency are required. In this study, a Class-J power amplifier was designed by optimizing an output matching circuit so that the second harmonic load will contain a pure reactance element only and have broadband characteristics by using GaN HEMT. The measurements showed that a 45 W Class-J power amplifier with a power added efficiency of 60~75 % was achieved when continuous wave signals were input at 1.6~2.3 GHz, including W-CDMA application.

• Journal of IKEEE
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• v.23 no.2
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• pp.425-430
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• 2019

This work describes the design and characterization of a X-band power amplifier (PA) monolithic microwave integrated circuit (MMIC) using a $0.25{\mu}m$ gate length gallium nitride (GaN) high electron mobility transistor (HEMT) technology. The developed X-band power amplifier MMIC has small signal gain of over 22.7 dB and saturated output power of 43.02 dBm (20.04 W) over the entire band of 9 to 10 GHz. Maximum saturated output power is a 43.84 dBm (24.21 W) at 9.5 GHz. Its power added efficiency (PAE) is 41.0~51.24% and the chip dimensions are $3.7mm{\times}2.3mm$, generating the output power density of $2.84W/mm^2$. The developed GaN power amplifier MMIC is expected to be applied in a variety of X-band radar applications.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.2C
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• pp.191-199
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• 2006

In this paper, we propose a method to implement a predistorter of the $rho$-th order inverse filter structure to prevent signal distortion and spectral re-growth due to the high PAPR (peak-to-average ratio) of the OFDM signals and the non-linearity of high-power amplifiers. We model the memory-less non-linearity of the high-power amplifier with a polynomial model and utilize the inverse of the model, the $rho$-th order inverse filter, for the predistorter. Once the non-linearity is modeled with a polynomial, since we can determine the $rho$-th order inverse filter only with the coefficients of the polynomial, large memory is not required. To update the coefficients of the non-linear high-power amplifier model, we can use LMS or RLS algorithms. The convergence speed is high since the number of coefficients is small, and the computation is simple since manipulation of complex numbers is not necessary.

• Journal of the Korea Institute of Military Science and Technology
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• v.12 no.4
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• pp.446-451
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• 2009

In this paper, we described the design and test results of a high output power amplifier MMIC developed by using 0.5um power pHEMT processes on a 6-inch GaAs wafer for the X-band T/R module application. In the MMIC design, we have used a simple on-chip gate active bias technology to compensate the threshold-voltage variation of pHEMT during the fabrication process and 16-to-1 power combining method to achieve the output power over 10watt. The fabricated chip has an output power over 12watts and maximum PAE of 32% over the frequency range of fo +/-750MHz.