• Journal of Korea Society of Industrial Information Systems
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• v.19 no.4
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• pp.17-24
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• 2014

In this paper, we propose a CMOS FM RX front-end structure with an automatic tunable input matching network and implement it using a 65nm CMOS technology. The proposed FM RX front-end is designed to change the resonance frequency of the input matching network at the low noise amplifier (LNA) according to the channel frequency selected by a phase-locked loop (PLL) for maintaining almost constant sensitivity level when an embedded antenna type with high frequency selectivity characteristic is used for FM receiver. The simulation results of implemented FM front-end show about 38dB of voltage gain, below 2.5dB of noise figure, and -15.5dBm of input referred intercept point (IIP3) respectively, while drawing only 3.5mA from 1.8V supply voltage including an LO buffer.

• IEIE Transactions on Smart Processing and Computing
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• v.5 no.1
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• pp.35-42
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• 2016

Developments in power electronics have enabled the widespread application of Pulse Width Modulation (PWM) inverters, notably for connecting renewable systems to the grid. This study demonstrates that a high-quality power can be achieved using a stand-alone inverter, whereby the comparison between the power quality of the stand-alone inverter with battery storage (off-grid) and the power quality of the utility network is presented. Multi-loop control techniques for a single phase stand-alone inverter are used. A capacitor current control is used to give active damping and enhance the transient and steady state inverter performance. A capacitor current control is cheaper than the inductor current control, where a small current sensing resistor is used. The output voltage control is used to improve the system performance and also control the output voltage. The inner control loop uses a proportional gain current controller and the outer loop is implemented using internal model control proportional-integral-derivative to ensure stability. The optimal controls are achieved by using the Sisotool tool in MATLAB/Simulink. The outcome of the control scheme of the numerical model of the stand-alone inverter has a smooth and good dynamic performance, but also a strong robustness to load variations. The numerical model of the stand-alone inverter and its power quality are presented, and the power quality is shown to meet the IEEE 519-2014. Furthermore, the power quality of the off-grid system is measured experimentally and compared with the grid power, showing power quality of off-grid system to be better than that of the utility network.

• Journal of Electrical Engineering and information Science
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• v.3 no.2
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• pp.239-244
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• 1998

Piezoelectric pressure sensors and pyroelectric infrared detectors based on ZnO thin film have been integrated with GaAs metal-semiconductor field effect transistor (MESFET) amplifiers. Surface micromachining techniques have been applied in a GaAs MESFET process to form both microsensors and electronic circuits. The on-chip integration of microsensors such as pressure sensors and infrared detectors with GaAs integrated circuits is attractive because of the higher operating temperature up to 200 oC for GaAs devices compared to 125 oC for silicon devices and radiation hardness for infrared imaging applications. The microsensors incorporate a 1${\mu}$m-thick sputtered ZnO capacitor supported by a 2${\mu}$m-thick aluminum membrane formed on a semi-insulating GaAs substrate. The piezoelectric pressure sensor of an area 80${\times}$80 ${\mu}$m2 designed for use as a miniature microphone exhibits 2.99${\mu}$V/${\mu}$ bar sensitivity at 400Hz. The voltage responsivity and the detectivity of a single infrared detector of an area 80${\times}$80 $\mu\textrm{m}$2 is 700 V/W and 6${\times}$108cm$.$ Hz/W at 10Hz respectively, and the time constant of the sensor with the amplifying circuit is 53 ms. Circuits using 4${\mu}$m-gate GaAs MESFETs are fabricated in planar, direct ion-implanted process. The measured transconductance of a 4${\mu}$m-gate GaAs MESFET is 25.6 mS/mm and 12.4 mS/mm at 27 oC and 200oC, respectively. A differential amplifier whose voltage gain in 33.7 dB using 4${\mu}$m gate GaAs MESFETs is fabricated for high selectivity to the physical variable being sensed.

• Progress in Superconductivity
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• v.7 no.1
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• pp.46-51
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• 2005

We have developed control electronics to operate flux-locked loop (FLL), and analog signal filters to process FLL outputs for 64-channel Double Relaxation Oscillation SQUID (DROS) magnetocardiography (MCG) system. Control electronics consisting of a preamplifier, an integrator, and a feedback, is compact and low-cost due to larger swing voltage and flux-to-voltage transfer coefficients of DROS than those of dc SQUIDs. Analog signal filter (ASF) serially chained with a high-pass filter having a cut-off frequency of 0.1 Hz, an amplifier having a gain of 100, a low-pass filter of 100 Hz, and a notch filter of 60 Hz makes FLL output suitable for MCG. The noise of a preamplifier in FLL control electronics is $7\;nV/{\surd}\;Hz$ at 1 Hz, $1.5\;nV/{\surd}\;Hz$ at 100 Hz that contributes $6\;fT/{\surd}\;Hz$ at 1 Hz, $1.3\;fT/{\surd}\;Hz$ at 100 Hz in readout electronics, and the noise of ASF electronics is $150\;{\mu}V/{\surd}\;Hz$ equivalent to $0.13\;fT/{\surd}\;Hz$ within the range of $1{\sim}100\;Hz$. When DROSs are connected to readout electronics inside a magnetically shielded room, the noise of 64-channel DROS system is $10\;fT/{\surd}\;Hz$ at 1 Hz, $5\;fT/{\surd}\;Hz$ at 100 Hz on the average, low enough to measure human MCG.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.941-944
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• 2015

In this paper study for VSAT(very small aperture terminal) LNB(low noise block). ship LNB was demanded high stability and low noise figure. We designed FEM(Front-End Module) that was operated multi-band. FEM designed was constructed in a multi-band low noise receiver amplifier, a frequency converter, IF amplifier, Voltage Control Oscillator signal generating circuit four circuit using. To convert the multi-band 2.05GHz band, it generates four local oscillator signals, the four(band1, band2, band3, band4) designed to output an IF signal developed conversion apparatus, the conversion gain 64dB, noise figure 1dB or less, output P1dB 15dBm or more, phase noise showed -73dBc@100Hz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.9
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• pp.31-39
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• 2011

In this paper, we propose a signal readout system with small area and low power consumption for CNT sensor arrays. The proposed system consists of signal readout circuitry, a digital controller, and UART I/O. The key components of the signal readout circuitry are 64 transimpedance amplifiers (TIA) and SAR-ADC with 11-bit resolution. The TIA adopts an active input current mirror (AICM) for voltage biasing and current amplification of a sensor. The proposed architecture can reduce area and power without sampling rate degradation because the 64 TIAs share a variable gain amplifier (VGA) which needs large area and high power due to resistive feedback. In addition, the SAR-ADC is designed for low power with modified algorithm where the operation of the lower bits can be skipped according to an input voltage level. The operation of ADC is controlled by a digital controller based on UART protocol. The data of ADC can be monitored on a computer terminal. The signal readout circuitry was designed with 0.13${\mu}m$ CMOS technology. It occupies the area of 0.173 $mm^2$ and consumes 77.06${\mu}W$ at the conversion rate of 640 samples/s. According to measurement, the linearity error is under 5.3% in the input sensing current range of 10nA - 10${\mu}A$. The UART I/O and the digital controller were designed with 0.18${\mu}m$ CMOS technology and their area is 0.251 $mm^2$.

• Transactions on Electrical and Electronic Materials
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• v.13 no.2
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• pp.73-77
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• 2012

Operation of liquid crystal displays (LCDs) can be improved by monolithic integration of the pixel transistors with light emitting diodes (LEDs) on a single substrate. Conventional LCDs make use of filters to control the backlighting which reduces the overall efficiency. These LCDs also utilize LEDs in series which impose failure and they require high voltage for operation with a power factor correction. The screen of small hand-held devices can operate from moderate brightness. Therefore, III-V nanowires that are grown along with transistors over Silicon substrates can be utilized. Control of nanowire LEDs with nanowire transistors will significantly lower the cost, increase the efficiency, improve the manufacturing yield and simplify the structure of the small displays that are used in portable devices. The steps to grow nanowires on Silicon substrates are described. The vertical n-type and p-type nanowire transistors with surrounding gate structures are characterized. While biased at 0.5 V, nanowire transistors with minimum radius or channel width have an OFF current which is less than 1pA, an ON current more than 1 ${\mu}A$, a total delay less than 10 ps and a transconductance gain of more than 10 ${\mu}A/V$. The low power and fast switching characteristics of the nanowire transistor make them an ideal choice for the realization of future displays of portable devices with long battery lifetime.

• Journal of the Korea Institute of Military Science and Technology
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• v.12 no.6
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• pp.760-767
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• 2009

This thesis focuses on the study of high-power, coupled-cavity traveling-wave tube(CCTWT) for radar applications. The CCTWT employed a reentrant double-slot staggered RF cavity structure. Computational analysis of the X-band, double-slot staggered structures is carried out through the use of HFSS code, which solves Maxwell's equations fully in three-dimensions. The non-linear, large-signal performance of CCTWTs are predicted from numerical simulations using a three-dimensional particle-in-cell code, MAGIC3D. With beam voltage set to 12.7~13kV and beam current at 300mA, the CCTWT produces a saturated radiation power of 350~430W, corresponding to an electronic efficiency of 8.9~11.2% and a gain of 23.7~24.2dB within a frequency range of 7.9~8.4GHz.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.235-245
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• 2014

This paper presents an envelope tracking power amplifier using a standard CMOS process for the 3GPP long-term evolution transmitters. An efficiency of the CMOS power amplifier for the modulated signals can be improved using a highly efficient and wideband CMOS bias modulator. The CMOS PA is based on a two-stage differential common-source structure for high gain and large voltage swing. The bias modulator is based on a hybrid buck converter which consists of a linear stage and a switching stage. The dynamic load condition according to the envelope signal level is taken into account for the bias modulator design. By applying the bias modulator to the power amplifier, an overall efficiency of 41.7 % was achieved at an output power of 24 dBm using the 16-QAM uplink LTE signal. It is 5.3 % points higher than that of the power amplifier alone at the same output power and linearity.

• Journal of IKEEE
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• v.18 no.1
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• pp.37-44
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• 2014

In this paper we present an LDO based on an error amplifier. The designed error amplifier has a gain of 89.93dB at low frequencies. This amplifier's Bandwidth is 50.8MHz and its phase margin is $59.2^{\circ}C$. Also we proposed a BGR. This BGR has a low output variation with temperature and its PSRR at 1 KHz is -71.5dB. For a temperature variation from $-40^{\circ}C$ to $125^{\circ}C$ we have just 9.4mV variation in 3.3V LDO output. Also it is stable for a wide range of output load currents [0-200mA] and a $1{\mu}F$ output capacitor and its line regulation and especially load regulation is very small comparing other papers. The PSRR of proposed LDO is -61.16dB at 1 KHz. Also we designed it for several output voltages by using a ladder of resistors, transmission gates and a decoder. Low power consumption is the other superiority of this LDO which is just 1.55mW in full load. The circuit was designed in $0.35{\mu}m$ CMOS process.