• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.1
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• pp.53-60
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• 2004

This work describes a l0b 150 MSample/s CMOS pipelined A/D converter (ADC) based on advanced bootsuapping techniques for higher input bandwidth than a sampling rate. The proposed ADC adopts a typical multi-step pipelined architecture, employs the merged-capacitor switching technique which improves sampling rate and resolution reducing by $50\%$ the number of unit capacitors used in the multiplying digital-to-analog converter. On-chip current and voltage references for high-speed driving capability of R & C loads and on-chip decimator circuits for high-speed testability are implemented with on-chip decoupling capacitors. The proposed AU is fabricated in a 0.18 um 1P6M CMOS technology. The measured differential and integral nonlinearities are within $-0.56{\~}+0.69$ LSB and $-1.50{\~}+0.68$ LSB, respectively. The prototype ADC shows the signal-to-noise-and-distortion ratio (SNDR) of 52 dB at 150 MSample/s. The active chip area is 2.2 mm2 (= 1.4 mm ${\times}$ 1.6 mm) and the chip consumes 123 mW at 150 MSample/s.

• Transactions of the Korean Society of Automotive Engineers
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• v.11 no.5
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• pp.163-169
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• 2003

Modeling of engine-generator system and its control responses are investigated using high performance generator controller. The nonlinear engine is modeled using mean torque production model based on experimental engine map. In case of diesel engine. the amount of injected fief is decided by engine controller depending on the APS(Acceleration Position Sensor) value. An electromechanical generator model contains electrical circuits and moment of inertia. The generator controller maximizes the performance of generator using decoupling and linearized current feedback control. The generator control system consists of 3-phase IGBT inverter and controller board based on 32 bit floating point DSP. Field oriented control algorithm with digital current feedback control at 10kHz sampling enabled high performance torque and speed control of induction machine. Not only the steady state but also the transient state responses can be evaluated through a batch test of the engine generator system. Developed engine and generator modeling and control can be utilized in various applications such as Series Hybrid Electric Vehicle(SHEV), engine-generator for emergency, and other hybrid generation systems.

• The Transactions of the Korean Institute of Power Electronics
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• v.9 no.1
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• pp.30-35
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• 2004

In a switched reluctance motor drive, it is important to synchronize the stator phase excitation with the rotor position, Therefore the position of rotor is an essential information. Although high resolution optical encoder/resolvers we used to provide a precise position information, these sensors are expensive. And switching angles synchronizing using sensorless technique has some problems like a reliability and fluctuating of the preset value in the high-speed region, which is caused by the sampling period of the microprocessor. In this paper, a low cost analog encoder suitable for practical applications is proposed. And the control algorithm to generate switching signals using a simple digital logic is presented. The validity of the proposed analog encoder with a proper logic controller is verified from the experiments.

• Korean Journal of Fisheries and Aquatic Sciences
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• v.43 no.6
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• pp.735-739
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• 2010

This study investigated a method for monitoring fishes immigrating to upper streams from the sea in relation to water level with elapsed time, and measured fish behavior patterns and swimming speed in a fishing boat gateway using an acoustic camera system. This method was employed due to difficulties, linked to high turbidity, of using only underwater optical systems for monitoring fish migrating to brackish water. Results showed that fish length distribution showed high correlation between haul sampling and an automatic counting algorithm supported by the DIDSON software program. These results will help to maximize the effects of fish run management by increasing understanding of the amount of major fish species migrating in relation to durable water levels.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2004.05b
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• pp.136-139
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• 2004

This thesis is realization of embedded system that of MPEG-2 down conversion using IDCT. A method for down conversion of MPEG compressed video is to perform low-pass filtering and sub-sampling after full decompression. However, this method is need large memory and high computational complexity. Recent research has been focussed on the down conversion in the DCT domain. But DCT method is reduced image qualify. The embedded system is require low complexity, and high speed algorithm. When applied to embedded system that down conversion method, DCT method is played average 29 frame per second, and better 25% than spatial-domain down conversion.

• Wind and Structures
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• v.28 no.4
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• pp.225-238
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• 2019

In this paper a novel and efficient computational framework to estimate the stress range versus number of cycles curves experienced by a cable due to external excitations (e.g., seismic excitations, traffic and wind-induced vibrations, among others) is proposed. This study is limited to the wind-cable interaction governed by the Vortex Shedding mechanism which mainly rules cables vibrations at low amplitudes that may lead to their failure due to bending fatigue damage. The algorithm relies on a stochastic approach to account for the uncertainties in the cable properties, initial conditions, damping, and wind excitation which are the variables that govern the wind-induced vibration phenomena in cables. These uncertainties are propagated adopting Monte Carlo simulations and the concept of importance sampling, which is used to reduce significantly the computational costs when new scenarios with different probabilistic models for the uncertainties are evaluated. A high fidelity cable model is also proposed, capturing the effect of its internal wires distribution and helix angles on the cables stress. Simulation results on a 15 mm diameter high-strength steel strand reveal that not accounting for the initial conditions uncertainties or using a coarse wind speed discretization lead to an underestimation of the stress range experienced by the cable. In addition, parametric studies illustrate the computational efficiency of the algorithm at estimating new scenarios with new probabilistic models, running 3000 times faster than the base case.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.2
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• pp.37-42
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• 2000

In this paper, The high-speed, low-Power analog-to-digital conversion structure is proposed using the pipelined comparator away for high-speed conversion rate and the successive- approximation structure for low-power consumption. This structure is the successive-approximation structure using pipelined comparator array to change the reference voltage during the holding time. An 8-bit 10MS/s analog-to-digital converter is designed using 0.8${\mu}{\textrm}{m}$ CMOS technology. The INL/DNL errors are $\pm$0.5/$\pm$1, respectively. The SNR is 41㏈ at a sampling rate of 10MHz with 100KHz sine input signal. The Power consumption is 4.14㎽ at 10MS/s.

• The Journal of the Acoustical Society of Korea
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• v.21 no.3
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• pp.293-303
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• 2002

This paper implements optimized Time Scale Modification (TSM) system using ITU G.729 speech decoder and Dual SOLA algorithm. The proposed system assume 8 Kz sampling rate, 80 samples/frame input speech from the ITU G.729 speech Decoder and the TSM (Time Scale Modification) feature of Dual SOLA produces the high quality output speech that was slow-down or speed up as a user's choice. Especially, the proposed Optimized Dual SOLA base on various simulations and theoretical analysis, and the additional interpolation procedure of the speech makes it possible to setup high performance integrated TSM system at the maximum time scale modification rate. The system performance is analyzed and verified with various input speech and playback speed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.11
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• pp.35-42
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• 2004

A CMOS folding ADC with transistor differential pair folding circuit for low power consumption and high speed operation is presented in this paper. This paper explains the theory of transistor differential pair folding technique and many advantages compared with conventional folding and interpolation circuits. A ADC based on transistor differential pair folding circuit uses 16 fine comparators and 32 interpolation resistors. So it is possible to achieve low power consumption, high speed operation and small chip size. Design technology is based on fully standard 0.25${\mu}{\textrm}{m}$ double poly 2 metal n-well CMOS process. A power consumption is 45mW at 2.5V applied voltage and 250MHz sampling frequency. The INL and DNL are within $\pm$0.15LSB and $\pm$0.15LSB respectively. The SNDR is approximately 50dB at 10MHz input frequency.

• The Transactions of the Korean Institute of Power Electronics
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• v.15 no.1
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• pp.43-51
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• 2010

This paper proposes an analysis of voltage delay and compensation for current control in H-Bridge Multi-Level (HBML) inverters for a medium voltage motor drive with vector control. It is shown that the expansion and modularization capability of the HBML inverter is improved in case of using Phase-Shifted Pulse Width Modulation (PSPWM) since individual inverter modules operate more independently. But, the PSPWM of HBML has a phase difference between reference voltage and real voltage, which can cause instability in the current regulator at high speed where the ratio of the sampling frequency to the output frequency is insufficient. This instability of the current regulator is removed by adding a proposed method which compensate a phase difference between reference voltage and real voltage. The proposed method is suitable for HBML inverter controlled by PSPWM with low switching frequency and high speed motor drive. The validity of the proposed method is verified experimentally on 6,600[V] 1,400[kW] induction motor fed by an 13-level HBML inverter.