• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.6
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• pp.1193-1199
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• 2015

Studies applying multiple carrier method such as OFDM(Orthogonal Frequency Division Multiplexing) or FMT(Filtered Multi-Tone) to Underwater acoustic communication(UAC) system are actively under way as UAC is utilized in the various fields and the demand of high speed data transmission increases. In the existing OFDM method, the use of virtual carrier, which is inserted not to affect the adjacent channel in the frequency domain, and the cyclic prefix, which is used to reduce the impact of Inter Symbol Interference and Inter Channel Interference, decrease the throughput. In particular, the length of cyclic prefix to be used becomes longer under water since underwater has a rapidly changing channel characteristic, and the data throughput diminishes because it has to allocate more subcarrier on virtual carrier. This study therefore suggests FMT-OFDM system, a combination of OFDM and FMT, for the purpose of enhanced throughput in the underwater channel environment. Besides, in this study, channel is modeled based on data measured in real sea and the performance is analyzed after setting system parameters.

• Management & Information Systems Review
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• v.28 no.3
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• pp.191-210
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• 2009

Internet was first designed only for sending data, but as the time passed, internet started to evolve into a broadband multi-media web that is capable of transmitting sound, video, high-capacity data and more due to the demands of internet users and the rapid changing internet-communication technology. Domestically, in January, 2000 Saerom C&T, launched a free VoIP, but due to limited ways of conversation(PC to PC) and absence of a revenue model, and bad speech quality, it had hit it's growth limit. This research studied VoIP based on technological enhancement in super-speed internet. According to IDC, domestic internet market's size was 80,800 million in 2008, and it formed a percentage of 12.5% out of the whole sound-communication market. in case of VoIP, it is able to maximize it's profit by connecting cable and wireless network, also it has a chance of becoming firm-concentrated monopoly market by fusing with IPTV. Considering the fact that our country is insignificant in MVNO revitalization, regulating organizations will play a significant roll on regulating profit between large and small businesses. Further research should be done to give VoIP a secure footing to prosper and become popularized.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.2
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• pp.72-77
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• 2009

In this paper, a 3.2Gb/s clock and data recovery (CDR) circuit for a high-speed serial data communication without the reference clock is described This CDR circuit consists of 5 parts as Phase and frequency detector(PD and FD), multi-phase Voltage Controlled-Oscillator(VCO), Charge-pumps (CP) and external Loop-Filter(KF). It is adapted the PD and FD, which incorporates a half-rate bang-bang type oversampling PD and a half-rate FD that can improve pull-in range. The VCO consists of four fully differential delay cells with rail-to-rail current bias scheme that can increase the tuning range and tuning linearity. Each delay cell has output buffers as a full-swing generator and a duty-cycle mismatch compensation. This materialized CDR can achieve wide pull-in range without an extra reference clock and it can be also reduced chip area and power consumption effectively because there is no additional Phase Locked- Loop(PLL) for generating reference clock. The CDR circuit was designed for fabrication using 0.18um 1P6M CMOS process and total chip area excepted LF is $1{\times}1mm^2$. The pk-pk jitter of recovered clock is 26ps at 3.2Gb/s input data rate and total power consumes 63mW from 1.8V supply voltage according to simulation results. According to test result, the pk-pk jitter of recovered clock is 55ps at the same input data-rate and the reliable range of input data-rate is about from 2.4Gb/s to 3.4Gb/s.

• The Journal of the Acoustical Society of Korea
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• v.14 no.2E
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• pp.91-97
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• 1995

This paper describes the implementation of a multi-channel audio codec for HETV. This codec has the features of the 3/2-stereo plus low frequency enhancement, downward compatibility with the smaller number of channels, backward compatibility with the existing 2/0-stereo system(MPEG-1 audio), and multilingual capability. The encoder of this codec consists of 6-channel analog audio input part with the sampling rate of 48 kHz, 4-channel digital audio input part and three TMS320C40 /DSPs. The encoder implements multi-channel audio compression using a human perceptual psychoacoustic model, and has the bit rate reduction to 384 kbit/s without impairment of subjective quality. The decoder consists of 6-channel analog audio output part, 4-channel digital audio output part, and two TMS320C40 DSPs for a decoding procedure. The decoder analyzes the bit stream received with bit rate of 384 kbit/s from the encoder and reproduces the multi-channel audio signals for analog and digital outputs. The multi-processing of this audio codec using multiple DSPs is ensured by high speed transfer of date between DSPs through coordinating communication port activities with DMA coprocessors. Finally, some technical considerations are suggested to realize the problem of real-time operation, which are found out through the implementation of this codec using the MPEG-2 layer II sudio coding algorithm and the use of the hardware architecture with commercial multiple DSPs.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.5
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• pp.83-93
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• 2013

Recently, the SURF algorithm, which is conjugated for object tracking system as part of many computer vision applications, is a well-known scale- and rotation-invariant feature detection algorithm. The SURF, due to its high computational complexity, there is essential to develop a hardware accelerator in order to be used on an IP in embedded environment. However, the SURF requires a huge local memory, causing many problems that increase the chip size and decrease the value of IP in ASIC and SoC system design. In this paper, we proposed a way to design a SURF algorithm in hardware with greatly reduced local memory by partitioning the algorithms into several Sub-IPs using external memory and a DMA. To justify validity of the proposed method, we developed an example of simplified object tracking algorithm. The execution speed of the hardware IP was about 31 frame/sec, the logic size was about 74Kgate in the 30nm technology with 81Kbytes local memory in the embedded system platform consisting of ARM Cortex-M0 processor, AMBA bus(AHB-lite and APB), DMA and a SDRAM controller. Hence, it can be used to the hardware IP of SoC Chip. If the image processing algorithm akin to SURF is applied to the method proposed in this paper, it is expected that it can implement an efficient hardware design for target application.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.12
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• pp.149-158
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• 2005

This paper proposes a congestion avoidance algorithm which provides stable throughput and transmission rate regardless of buffer size by limiting the TCP congestion window in fixed bandwidth networks. Additive Increase, Multiplicative Decrease (AIMD) is the most commonly used congestion control algorithm. But, the AIMD-based TCP congestion control method causes unnecessary packet losses and retransmissions from the congestion window increment for available bandwidth verification when used in fixed bandwidth networks. In addition, the saw tooth variation of TCP throughput is inappropriate to be adopted for the applications that require low bandwidth variation. We present an algorithm in which congestion window can be limited under appropriate circumstances to avoid congestion losses while still addressing fairness issues. The maximum congestion window is determined from delay information to avoid queueing at the bottleneck node, hence stabilizes the throughput and the transmission rate of the connection without buffer and window control process. Simulations have performed to verify compatibility, steady state throughput, steady state packet loss count, and the variance of congestion window. The proposed algorithm can be easily adopted to the sender and is easy to deploy avoiding changes in network routers and user programs. The proposed algorithm can be applied to enhance the performance of the high-speed access network which is one of the fixed bandwidth networks.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.13 no.3
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• pp.78-88
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• 2014

Now, UTIS collects and provides traffic information by building RSE 1,150(unit) and OBE about 51,000(vehicle). it's inevitable to enlarge traffic information sources which use to improve quality of UTIS traffic information for Stabilizing UTIS's service. but there are missing data sections. And, In this study as a way to overcome these problems, based on BIS(Bus information system) installed and operating in the capital area to develop normal vehicle's link transit time estimation model which is used realtime collecting BMS data, we'll utilize the model to provide missing data section's information. For these problem, we selected partial section of suwon-city, anyang-city followed by drive only way or not and conducted model estimating and verification each of BMS data and UTIS traffic information. Consequently, Case2,4,6,8 presented highly credibility between UTIS communication data and estimated value but In the Case 3,5 we determined to replace communication data of UTIS' missing data section too hard for large error. So we need to apply high credibility model formula adjusting road managing condition and the situation of object section.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.6
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• pp.609-616
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• 2017

In this paper, we propose an algorithm to obtain more stable and high recognition rate by using left and right rotation information of input image in order to obtain a stable recognition rate in face recognition. The proposed algorithm uses the facial image as the input information in the web camera environment to reduce the size of the image and normalize the information about the brightness and color to obtain the improved recognition rate. We apply Principal Component Analysis (PCA) to the detected candidate regions to obtain feature vectors and classify faces. Also, In order to reduce the error rate range of the recognition rate, a set of data with the left and right $45^{\circ}$ rotation information is constructed considering the directionality of the input face image, and each feature vector is obtained with PCA. In order to obtain a stable recognition rate with the obtained feature vector, it is after scattered in the eigenspace and the final face is recognized by comparing euclidean distant distances to each feature. The PCA-based feature vector is low-dimensional data, but there is no problem in expressing the face, and the recognition speed can be fast because of the small amount of calculation. The method proposed in this paper can improve the safety and accuracy of recognition and recognition rate faster than other algorithms, and can be used for real-time recognition system.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.5
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• pp.359-369
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• 2020

In this paper, we proposed a charge pump (CP) circuit that has a wide operating range while reducing the current mismatch for the PLL that generates the main clock of the CMOS X-Ray detector. The operating range and current mismatch of the CP circuit are determined by the characteristics of the current source circuit for the CP circuit. The proposed CP circuit is implemented with a wide operating current mirror bias circuit to secure a wide operating range and a cascode structure with a large output resistance to reduce current mismatch. The proposed wide operating range cascode CP circuit was fabricated as a chip using a 350nm CMOS process, and current matching characteristics were measured using a source measurement unit. At this time, the power supply voltage was 3.3 V and the CP circuit current ICP = 100 ㎂. The operating range of the proposed CP circuit is △VO_Swing=2.7V, and the maximum current mismatch is 5.15 % and the maximum current deviation is 2.64 %. The proposed CP circuit has low current mismatch characteristics and can cope with a wide frequency range, so it can be applied to systems requiring various clock speed.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.11
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• pp.4460-4467
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• 2010

Recent advances in computer technology have brought more dependence on software to railway systems and changed to computer systems. Hence, the reliability and safety assurance of the vital software running on the embedded railway system is going to tend toward very critical task. Accordingly, various software test and validation activities are highly recommended in the international standards related railway software. In this paper, we presented an automated analysis tool and standard for software testing coverage in railway system, and presented its result of implementation. We developed the control flow analysis tool estimating test coverage as an important quantitative item for software safety verification in railway software. Also, we proposed judgement standards due to railway S/W Safety Integrity Level(SWSIL) based on analysis of standards in any other field for utilizing developed tool widely at real railway industrial sites. This tool has more advantage of effective measuring various test coverages than other countries, so we can expect railway S/W development and testing technology of real railway industrial sites in Korea.