• Title/Summary/Keyword: High speed·high efficient

Search Result 1,160, Processing Time 0.031 seconds

A Novel Scalable and Storage-Efficient Architecture for High Speed Exact String Matching

  • Peiravi, Ali;Rahimzadeh, Mohammad Javad
    • ETRI Journal
    • /
    • v.31 no.5
    • /
    • pp.545-553
    • /
    • 2009
  • String matching is a fundamental element of an important category of modern packet processing applications which involve scanning the content flowing through a network for thousands of strings at the line rate. To keep pace with high network speeds, specialized hardware-based solutions are needed which should be efficient enough to maintain scalability in terms of speed and the number of strings. In this paper, a novel architecture based upon a recently proposed data structure called the Bloomier filter is proposed which can successfully support scalability. The Bloomier filter is a compact data structure for encoding arbitrary functions, and it supports approximate evaluation queries. By eliminating the Bloomier filter's false positives in a space efficient way, a simple yet powerful exact string matching architecture is proposed that can handle several thousand strings at high rates and is amenable to on-chip realization. The proposed scheme is implemented in reconfigurable hardware and we compare it with existing solutions. The results show that the proposed approach achieves better performance compared to other existing architectures measured in terms of throughput per logic cells per character as a metric.

An Experimental Study on the Determination of Efficient Superfinishing Conditions Using Polishing Film (연마필름을 이용한 효율적인 수퍼피니싱 조건의 결정에 관한 실험적 연구)

  • Jung, Sung-Yong;Park, Ki-Beom;Jung, Yoon-Gyo;Jung, Soo-Yong
    • Journal of the Korean Society for Precision Engineering
    • /
    • v.26 no.8
    • /
    • pp.55-61
    • /
    • 2009
  • Recently, many studies are being conducted to realize high quality polishing technology, but because of high dependence on field experience and insufficient research for ultra-precision polishing technology, it is difficult to establish standardization of polishing conditions. The purpose of this study is to determine high-efficiency superfinishing conditions which are applicable in the field of machining. To achieve this, we have a developed a superfinishing device and conducted a series of polishing experiments for mechanical materials such as SM45C, Brass, Al7075, and Ti, from the perspective of oscillation speed, the rotational speed of the workpiece, contact roller hardness, contact pressure, and feed rate. From the experimental results, it was confirmed that the polishable superfinishing conditions range and efficient feed rate of polishing film can be determined.

The design and performance evaluation of a high-speed cell concentrator/distributor with a bypassing capability for interprocessor communication in ATM switching systems (ATM교환기의 프로세서간 통신을 위한 바이패싱 기능을 갖는 고속 셀 집속/분배 장치의 설계 및 성능평가)

  • 이민석;송광석;박동선
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.22 no.6
    • /
    • pp.1323-1333
    • /
    • 1997
  • In this paper, we propose an efficient architecture for a high-speed cell concentrator/distributor(HCCD) in an ATM(Asynchronous Transfer Mode) switch and by analyzeing the simulation results evaluate the performance of the proposed architecuture. The proposed HCCD distributes cells from a switch link to local processors, or concentrates cells from local processor s to a switch link. This design is to guarntee a high throughput for the IPC (inter-processor communication) link in a distributed ATM switching system. The HCCD is designed in a moudlar architecture to provide the extensibility and the flexibility. The main characteristics of the HCCD are 1) Adaption of a local CPU in HCCD for improving flexibility of the system, 2) A cell-baced statistical multiplexing function for efficient multiplexing, 3) A cell distribution function based on VPI(Virtual Path Identifier), 4) A bypassing capability for IPC between processor attached to the same HCCD, 5) A multicasting capability for point-to-multipoint communication, 6) A VPI table updating function for the efficient management of links, 7) A self-testing function for detecting system fault.

  • PDF

Center Compensation Servo and Eccentric Compensation Control for High Speed CD-RW Drive System (고배속 CD-RW Drive를 위한 중점 서보 및 편심 보상 제어)

  • Kim Dongwon;Park Gwi-Tae;Seo Sam-Jun
    • Journal of Institute of Control, Robotics and Systems
    • /
    • v.10 no.12
    • /
    • pp.1202-1209
    • /
    • 2004
  • This paper presents a design methodology of a Digital Servo Signal Processor for high speed CD-RW drive systems. The proposed Digital Servo Signal Processor enables us to develop CD-related systems for the very high speed applications and is one of the key components of the CD-RW systems. The proposed center compensation servo control is newly built for an actuator shaking due to the fast response of a step motor when it jumps to a long distance. A control method compensating for eccentricity of a disc is implemented for operating robustly at a higher rotational speed. This servo mechanism is more size efficient and less power consumed because it is implemented using a ARM7 embedded processor and hardware digital filters. Furthermore, it is convenient to upgrade firmware for the future required functions. From experimental results, we can see that the performance of the control system is improved greatly. The proposed servo algorithm shows a shorter setting time including a pull-in time and a faster access time. It can be applied easily to the DVD-ROM and the DVD-RAM which have the same optical structure.

Resource Allocation Scheme in an Integrated CDMA System Using Throughput Maximization Strategy (통합된 CDMA시스템에서 데이터 전송률 최대화 방법을 이용한 자원할당 방법)

  • Choi Seung-Sik;Kim Sang-Kyung
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.31 no.2B
    • /
    • pp.146-153
    • /
    • 2006
  • It is required to have researches on efficient resource allocation schemes in an integrated voice and data CDMA system with the spreading of high-speed wireless internets. In this paper, we proposed a efficient resouce allocation scheme for providing a high speed data service in an integrated CDMA system. In an integrated voice/data CDMA system, resources for voice users are allocated with high priority and residual resources are allocated to the data service. In this case, it is necessary to use a resource allocation scheme for minimizing interference. In this paper, we first explain about a interference minimizing method and define QoS requirements. Based on the method, we proposed a efficient resource allocation scheme which satisfy the QoS requirements. The proposed scheme controls the transmission rate and delay of data users with a priority information such as the number of packets in a queue. From the simulation results, we show that the proposed scheme reduce the blocking probability and delay and improve the performance.

The Design and Implementation of Frequency Domain Sampling Surface Acoustic Wave Sensor Platform (Frequency Domain Sampling 방식의 Surface Acoustic Wave Sensor Platform 설계 및 구현)

  • Joh, Yool-Hee;Kim, Young-Kil
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
    • /
    • 2012.05a
    • /
    • pp.220-223
    • /
    • 2012
  • Generally, SAW device, which uses Time Domain Sampling, requires high speed AD converter because SAW device (TDS) needs high sampling speed as much as its high data speed. However, the high price of AD converter discourages makers from using it. On the other hand, SAW device, which uses Frequency Domain Sampling, does not required high speed AD converter because SAW device (FDS) does not need high sampling speed. It is very efficient in price comparison to its performance because high processing speed of SAW device (FDS) can be implemented using low price Embedded Systems. The purpose of the thesis is to solve the issues above by designing and realizing SAW device (FDS) using SAW sensor for TDS.

  • PDF

The Design and Implementation of Frequency Domain Sampling Surface Acoustic Wave Sensor Platform using Cortex-A8 (Cortex-A8을 이용한 Frequency Domain Sampling 방식의 Surface Acoustic Wave Sensor Platform 설계 및 구현)

  • Joh, Yool-hee;Kim, Young-kil
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
    • /
    • 2012.10a
    • /
    • pp.312-315
    • /
    • 2012
  • Generally, SAW device, which uses Time Domain Sampling, requires high speed AD converter because SAW device (TDS) needs high sampling speed as much as its high data speed. However, the high price of AD converter discourages makers from using it. On the other hand, SAW device, which uses Frequency Domain Sampling, does not required high speed AD converter because SAW device (FDS) does not need high sampling speed. It is very efficient in price comparison to its performance because high processing speed of SAW device (FDS) can be implemented using low price Embedded Systems. The purpose of the thesis is to solve the issues above by designing and realizing SAW device (FDS) using SAW sensor for TDS.

  • PDF

The Design and Implementation of Frequency Domain Sampling Method for Surface Acoustic Wave Sensor Platform (주파수 영역 샘플링 방식의 표면 탄성파 센서 플랫폼 설계 및 구현)

  • Sun, Hee-Gab;Joh, Yool-Hee;Kim, Young-Kil
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.17 no.1
    • /
    • pp.218-224
    • /
    • 2013
  • Generally, SAW device, which uses Time Domain Sampling, requires high speed A/D converter because SAW device using TDS needs high sampling speed as much as its high data speed. However, the high price of A/D converter discourages makers from using it. On the other hand, SAW device, which uses Frequency Domain Sampling, does not required high speed A/D converter because SAW device using FDS does not need high sampling speed. It is very efficient in price comparison to its performance because high processing speed of SAW device using FDS can be implemented using low price Embedded Systems. The purpose of the paper is to solve the issues above by designing and realizing SAW device(FDS) using SAW sensor for TDS.

An Efficient Method to Obtain Wind Speed Gradient with Low PRF Radar

  • 이종길
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.8 no.1
    • /
    • pp.28-33
    • /
    • 2004
  • The measurement of wind speed gradient is very important for the detection of hazardous wind shear conditions since they are characterized by the abrupt shift of wind velocity and direction. These weather conditions usually imply high wind speed which requires a high PRF radar for the measurement. However, the measurement of a large absolute wind velocity is not necessary to obtain wind speed gradient. In this paper, a method was proposed to obtain wind speed gradient with a simple low PRF radar which may be very useful for the purpose of practical applications.

An Efficient ACS Architecture for radix-4 Viterbi Decoder (Radix-4 비터비 디코더를 위한 효율적인 ACS 구조)

  • Kim Deok-Hwan;Rim Chong-Suck
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.42 no.1
    • /
    • pp.69-77
    • /
    • 2005
  • The Viterbi decoder which is used for the forward error correction(FEC) is a crucial component for successful modern communication systems. As modern communication speed rapidly high, the development of high speed communication module is important. However, since the feedback loop in ACS operation, high speed of Viterbi decoder is very difficult. In this paper, we propose an area reduced, high speed ACS Architecture of Viterbi decoder based on the radix-4 architecture. The area is reduced by rearranging the ACS operations, and the speed is improved by retiming of path metric memory. The proposed ACS architecture of Viterbi decoder is implemented in VHDL and synthesized in Xilinx ISE 6.2i. The area-time product of the proposed architecture is improved by 11% compared to that of the previous high speed radix-4 ACS architecture.