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An Efficient ACS Architecture for radix-4 Viterbi Decoder  

Kim Deok-Hwan (Department of Computer Science, Sognag University)
Rim Chong-Suck (Department of Computer Science, Sognag University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.42, no.1, 2005 , pp. 69-77 More about this Journal
Abstract
The Viterbi decoder which is used for the forward error correction(FEC) is a crucial component for successful modern communication systems. As modern communication speed rapidly high, the development of high speed communication module is important. However, since the feedback loop in ACS operation, high speed of Viterbi decoder is very difficult. In this paper, we propose an area reduced, high speed ACS Architecture of Viterbi decoder based on the radix-4 architecture. The area is reduced by rearranging the ACS operations, and the speed is improved by retiming of path metric memory. The proposed ACS architecture of Viterbi decoder is implemented in VHDL and synthesized in Xilinx ISE 6.2i. The area-time product of the proposed architecture is improved by 11% compared to that of the previous high speed radix-4 ACS architecture.
Keywords
VLSI design; Viterbi decoding; high speed architecture;
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