• Electrical & Electronic Materials
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• v.8 no.5
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• pp.626-632
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• 1995

In this paper, The effect of the impedances in SNOSFET's memory devices has been developed. The effect of source and drain impedances measured by means of two bias resistances - field effect bias resistance by inner region, external bias resistance. The effect of the impedances by source and drain resistance shows the dependence of the function of voltages applied to the gate. It shows the differences of change in source drain voltage by means of low conductance state and high conductance state. It shows the delay of threshold voltages. The delay time of low conductance state and high conductance state by the impedances effect shows 3[.mu.sec] and 1[.mu.sec] respectively.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.340-340
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• 2012

최근 MOS 소자들이 게이트 산화막을 Mono-layer가 아닌 Multi-Layer을 사용하는 추세이다. Bulk와 High-k물질간의 Dangling Bond를 줄이기 위해 Passivation 층을 만드는 것을 예로 들 수 있다. 이러한 Double Layer의 쓰임이 많아지면서 계면에서의 Interface State Density의 영향도 커지게 되면서 이를 측정하는 방법에 대한 연구가 활발히 진행되고 있다. 본 연구에서는 $SiO_2$ Double Layer의 Interface State Density를 Conductance Method를 사용하여 구하는 연구를 진행하였다. Wet Oxidation과 Chemical Vapor Deposition (CVD) 공정을 이용하여 $SiO_2$ Double-layer로 증착한 후 Aluminium을 전극으로 하는 MOS-Cap 구조를 만들었다. 마지막 공정은 $450^{\circ}C$에서 30분 동안 Forming-Gas Annealing (FGA) 공정을 진행하였다. LCR meter를 이용하여 high frequency C-V를 측정한 후 North Carolina State University California Virtual Campus (NCSU CVC) 프로그램을 이용하여 Flatband Voltage를 구한 후에 Conductance Method를 측정하여 Dit를 측정하였다. 본 연구 결과 Double layer (Wet/CVD $SiO_2$)에 대해서 Conductance Method를 방법을 이용하여 Dit를 측정하는 것이 유효하다는 것을 확인 할 수 있었다. 본 실험은 앞으로 많이 쓰이고 측정될 Double layer (Wet/CVD $SiO_2$)에 대한 Interface State Density의 측정과 분석에 대한 방향을 제시하는데 도움이 될 것이라 판단된다.

• 한국초전도학회:학술대회논문집
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• v.10
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• pp.85-85
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• 2000

The normal state of high-Tc superconducting materials has been believed to contain important clues to finding the correct mechanism of the high-Tc superconductivity. One example is the existence of pseudogap in the normal state even above Tc, as observed in various measurements such as photoemission spectroscopy and tunneling conductance. In this pseudogap regime the existence of preformed pairs only with local phase coherence has been debated. Recently Choi, Bang, and Campbell[1] have proposed the occurrence of the zero-bias conductance enhancement due to Andreev quasiparticle reflection from the preformed pairs even with the local phase coherence. In this study we examine the zero-bias enhancement of the differential conductance near or slightly above Tc, using c-axis tunneling in mesa structure of Bi2Sr20a0u208+d single crystals. In slightly overdoped samples zero-bias conductance enhancement (ZBCE) has been observed over a range of 2 K above Tc. In contrast, in underdoped samples with Tc${\sim}$72K the ZBCE appears over a range of 5-6 K above Tc, a much wider temperature range than in overdoped samples. This result may pose as positive signs of the existence of prefurmed pairs in the normal state of high- Tc superconducting materials.

• Proceedings of the KIPE Conference
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• 2016.07a
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• pp.185-186
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• 2016

Maximum power point tracking (MPPT) techniques play a big role in improving the efficiency of photovoltaic (PV) system. Among various schemes, the incremental conductance (INC) method is mostly discussed in literature because of its fast response to the rapid irradiation changes and high tracking accuracy. However, the existing INC algorithm has trade-offs between fast dynamic response and steady state stability. This study proposes a novel INC method to meet high efficiency and fast tracking performance at the same time.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1991.10a
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• pp.48-51
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• 1991

Short channel Nonvolatile EEPROM memory devices were fabricated to CMOS 1M bit design rule, and reviews the characteristics and applications of SNOSFET. Application of SNOS field effect transistors have been proposed for both logic circuits and nonvolatile memory arrays, and operating characteristics with write and erase were investigated. As a results, memory window size of four terminal devices and two terminal devices was established low conductance stage and high conductance state, which was operated in “1” state and “0”state with write and erase respectively. And the operating characteristics of unit cell in matrix array were investigated with implementing the composition method of four and two terminal nonvolatile memory cells. It was shown that four terminal 2${\times}$2 matrix array was operated bipolar, and two termineal 2${\times}$2 matrix array was operated unipolar.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1995.05a
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• pp.86-89
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• 1995

In this pacer, The effect of the impedances in SNOSEFT s memory devices has been developed. The effect of source and drain impedances are measuring using the method of the field effect bias resistance in the inner resistance regions of the device structure and external bias resistance. The effect of impedance by source and drain resistance shows according to increasing to the storage of memory charges, shows according to a function of decreasing to the gate voltages, shows the delay of threshold voltages, The delay time of low conductance state and high conductance state by the impedance effect shows 3 [${\mu}$sec] and 1[${\mu}$sec] respectively.

• 한국초전도학회:학술대회논문집
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• v.10
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• pp.141-144
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• 2000

We report on the influence of d-wave pairing symmetry in high-T$_c$ superconductor by tunneling spectroscopy. The zerobias conductance peak(ZBCP) which is produced by tunneling through the ab-plane is observed on both of metal Au/YBa$_2$Cu$_3$O$_y$(N/S) tunnel junctions and ferromagnet Co/Au/ YBa$_2$Cu$_3$O$_y$(F/N/S) tunnel junctions. The effects of Andreev reflection on the differential conductance of each junctions are dependent on the tunnel direction. For the S/N/F junction, it appears the suppression of the ZBCP due to the suppression of Andreev reflection at the interface between a ferromagnetic material and a d-wave superconductor. By comparing these experimental results with recent theoretical works on Andreev reflection, the existence of Andreev bound state is verified in high-T$_c$ superconductor, due to the d-wave symmetry of the pair potential.

• Journal of Hydrogen and New Energy
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• v.24 no.3
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• pp.206-215
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• 2013

A linear engine has advantages in terms of volume and weight, because there are no rotating parts. Thus, it is considered that linear engines might be suitable in hybrid vehicles. However, the linear engine has challenges in terms of the engine ignition timing and efficiency, so the engine has not been commercialized yet. In this study, the dynamic and combustion characteristics of the linear engine might be specified by various loads which are changed by conductance. The engine used in this experiment consists of two combustion chambers, four compressors, two linear alternators and a mover with a piston head and magnets. The way fuel is supplied in the experiment is by propane fuel being mixed with air in the carburetor, then being delivered into combustion cylinders via compressors. In the experiment, conductance is altered from 0.04 to 0.16mho, and the ignition timing is ahead by just 5.0mm from the maximum stroke. As a result of the experiment, frequency, stroke, input calories and maximum pressure are decreased when the conductance is increased. Meanwhile, IMEP, generation efficiency and electric power are increased when the conductance is increased. Therefore, it might confirm that high conductance generates more efficient electric power, but that thermal efficiency is the highest in the state of 0.08mho.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1992.05a
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• pp.91-96
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• 1992

The nonvolatile SNOSFET EEPROM memory devices with the channel width and iength of 15[$\mu\textrm{m}$]${\times}$15[$\mu\textrm{m}$], 15[$\mu\textrm{m}$]${\times}$1.5[$\mu\textrm{m}$] and 1.9[$\mu\textrm{m}$]${\times}$1.7[$\mu\textrm{m}$] were fabricated by using the actual CMOS 1 [Mbit] process technology. The charateristics of I$\_$D/-V$\_$D/, I$\_$D/-V$\_$G/ were investigated and compared with the channel width and length. From the result of measuring the I$\_$D/-V$\_$D/ charges into the nitride layer by applying the gate voltage, these devices ere found to have a low conductance state with little drain current and a high conductance state with much drain current. It was shown that the devices of 15[$\mu\textrm{m}$]${\times}$15[$\mu\textrm{m}$] represented the long channel characteristics and the devices of 15[$\mu\textrm{m}$]${\times}$1.5[$\mu\textrm{m}$] and 1.9[$\mu\textrm{m}$]${\times}$1.7[$\mu\textrm{m}$] represented the short channel characteristics. In the characteristics of I$\_$D/-V$\_$D/, the critical threshold voltages of the devices were V$\_$w/ = +34[V] at t$\_$w/ = 50[sec] in the low conductance state, and the memory window sizes wee 6.3[V], 7.4[V] and 3.4[V] at the channel width and length of 15[$\mu\textrm{m}$]${\times}$15[$\mu\textrm{m}$], 15[$\mu\textrm{m}$]${\times}$1.5[$\mu\textrm{m}$], 1.9[$\mu\textrm{m}$]${\times}$1.7[$\mu\textrm{m}$], respectively. The positive logic conductive characteristics are suitable to the logic circuit designing.

• Progress in Superconductivity
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• v.2 no.1
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• pp.43-46
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• 2000

We report on the tunneling spectroscopy of tunnel junctions using d-wave superconductor in relation to Andreev reflection. The zero bias conductance peak (ZBCP) which has maximum on [110] direction of ab-plane is observed on metal $Au/YBa_2Cu_3O_y$ tunnel junctions while it is suppressed on the ferromagnetic $Co/Au/YBa_2Cu_3O_y$ tunnel junctions. The effects of Andreev reflection on the differential conductance of each junction are dependent on the tunnel direction. For the $Co/Au/YBa_2Cu_3O_y$ junction, the suppression of Andreev reflection takes place by spin-polarized quasiparticles tunneling from a ferromagnetic material to a d-wave superconductor. By comparing these experimental results with recent theoretical works on Andreev reflection, the existence of Andreev bound state due to the d-wave symmetry of the pair potential is verified in high-$T_c$ superconductor.