• The KIPS Transactions:PartA
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• v.11A no.2
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• pp.195-202
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• 2004

This paper introduces the design or parallel Pipeline high-speed analog-to-digital converter(ADC) for the high-resolution video applications which require very precise sampling. The overall architecture of the ADC consists of 4-channel parallel time-interleaved 10-bit pipeline ADC structure a]lowing 200MSample/s sampling speed which corresponds to 4-times improvement in sampling speed per channel. Key building blocks are composed of the front-end sample-and-hold amplifier(SHA), the dynamic comparator and the 2-stage full differential operational amplifier. The 1-bit DAC, comparator and gain-2 amplifier are used internally in each stage and they were integrated into single switched capacitor architecture allowing high speed operation as well as low power consumption. In this work, the gain of operational amplifier was enhanced significantly using negative resistance element. In the ADC, a delay line Is designed for each stage using D-flip flops to align the bit signals and minimize the timing error in the conversion. The converter has the power dissipation of 280㎽ at 3.3V power supply. Measured performance includes DNL and INL of +0.7/-0.6LSB, +0.9/-0.3LSB.

• Transactions on Electrical and Electronic Materials
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• v.17 no.5
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• pp.261-269
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• 2016

A high-performance transmit/receive (T/R) switch is essential for every radio-frequency (RF) device. This paper proposes a T/R switch that is designed in the CEDEC 0.13 μm complementary metal-oxide-semiconductor (CMOS) technology for 2.4 GHz ISM-band RF applications. The switch exhibits a 1 dB insertion loss, a 28.6 dB isolation, and a 35.8 dBm power-handling capacity in the transmit mode; meanwhile, for the 1.8 V/0 V control voltages, a 1.1 dB insertion loss and a 19.4 dB isolation were exhibited with an extremely-low power dissipation of 377.14 μW in the receive mode. Besides, the variations of the insertion loss and the isolation of the switch for a temperature change from - 25℃ to 125℃ are 0.019 dB and 0.095 dB, respectively. To obtain a lucrative performance, an active inductor-based resonant circuit, body floating, a transistor W/L optimization, and an isolated CMOS structure were adopted for the switch design. Further, due to the avoidance of bulky inductors and capacitors, a very small chip size of 0.0207 mm² that is the lowest-ever reported chip area for this frequency band was achieved.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.12 no.4
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• pp.61-68
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• 2013

As an advance study for the development of a heat sink for special purpose high power illumination, an investigation was made to find feasibility for the application of copper plated EP to a heat sink of small LED light of less than 10W installed in commercial product. In this study, the plated heat sink with EP copper was fabricated for the conventional LED light. It was used actually for finding heat radiation property and effectiveness of the heat sink accompanied with measurement of luminous intensity. The heat is radiated by transfer and dissipation only through the copper plated surface due to extremely low heat conductivity of EP in case of EP heat sink; however the total area of the plate plays the function of heat transfer as well as heat radiation in case of the aluminum heat sink. It seems that the volume difference of heat radiating material is so big that the temperature $P_1$ is 9.0~12.3% higher in 3W and 42.7~54.0% higher in case of 6W volume difference of heat radiating material is so big that the temperature $P_1$ is 9.0~12.3% higher in 3W and 42.7~54.0% higher in case of 6W even though heat transfer rate of copper is approximately 1.9 times higher than that of aluminum. It was thought that this is useful to utilize for heat sink for low power LED light with the low heating rate. Also, the illumination could be greatly influenced by the surrounding temperature of the place where it is installed. Therefore, it seems that the illumination installation environment must be taken into consideration when selecting illumination. Further study was expected on order to aims at development of an exterior surface itself made into heat radiation plate by application of this technology in future.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.10
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• pp.64-71
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• 2014

Multiplier performs a complex arithmetic operation in various signal processing algorithms such as multimedia and communication system. The multiplier also suffers from its relatively large signal propagation delay, high power dissipation, and large area requirement. This paper presents memristor-CMOS based reconfigurable multiplier reducing area occupation of the multiplier circuitry and increasing compatibility using optimized bit-width for various applications. The performance of the memristor-CMOS based reconfigurable multiplier are estimated with memristor SPICE model and 180 nm CMOS process under 1.8 V supply voltage. The circuit shows performance improvement of 61% for area, 38% for delay and 28% for power consumption respectively compared with the conventional reconfigurable multipliers. It also has an advantage for area reduction of 22% against a twin-precision multiplier.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.12
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• pp.20-26
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• 1999

A CMOS 6-bit 100MSPS ADC for DBS receiver is designed. The proposed ADC is composed of folding block, latch block, and digital block. The cascode interpolating block and kickback reduced latch are proposed with a high speed architecture. To verify the performance of ADC, simulations are carried out by HSPICE. The ADC achieves a clock frequency of 100MHz with a power dissipation of 40mW for 3 V supply voltage. The active chip area is $1500{\mu}m{\times}1000{\mu}m$with $0.65{\mu}m$ 2-poly 2-metal CMOS process. Further, INL and DNL are within ${\pm}0.6LSB$, ${\pm}0.5LSB$, respectively. SNDR is about 33dB at 10MHz input frequency.

• Journal of the Microelectronics and Packaging Society
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• v.23 no.4
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• pp.35-41
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• 2016

Ceramic-metal based high power LED array package was developed via thick film LTCC technology using a glass-ceramic insulation layer and a silver conductor patterns directly printed on the aluminum heat sink substrate. The thermal resistance measurement using thermal transient tester revealed that ceramic-metal base LED package exhibited a superior heat dissipation property to compare with the previously known packaging method such as FR-4 based MCPCB. A prototype LED package sub-module with 50 watts power rating was fabricated using a ceramic-metal base chip-on-a board technology with minimized camber deformation during heat treatment by using partially covered glass-ceramic insulation layer design onto the aluminum heat spread substrate. This modified circuit design resulted in a camber-free packaging substrate and an enhanced heat transfer property compared with conventional MCPCB package. In addition, the partially covered design provided a material cost reduction compared with the fully covered one.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.43 no.4 s.310
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• pp.53-59
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• 2006

This paper describes the new design technique of full wave rectifier (FWR) for precise measurement instrument and the chip implementation of this FWR circuit with measurement results. Conventional circuits have some problems of complex design and limited output range( $VDD/2{\sim}VLIIV1IT+$). Proposed FWR circuit was simply designed with two 2x1 MUXs, one high speed comparator, and one differential difference amplifier(DDA). One rail-to-rail differential difference amplifier(DDA) performs the DC level shifting to VSS and 2X amplification simultaneously, and enables the full range ($Vss{\sim}VDD$) operation. The proposed FWR circuits shows more than 50% reduction of chip area and power consumption compared to conventional one. Proposed circuit was implemented with 0.35um 1-poly 2-metal CMOS process. Core size is $150um{\times}450um$ and power dissipation is 840uW with 3.3V single supply.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.44 no.4
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• pp.373-379
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• 2016

The thermal control device for the periodic working component combined solid-liquid phase change material (PCM) with heat pipes is designed and numerically studied. Due to high latent heat and retaining constant temperature during melting process the component peak temperature, not withstanding small radiator size, is reduced. The warm-up heater power consumption to keep the minimum allowed temperature is also cut down since the accumulated thermal energy is released through the solidification. The thermal buffer mass (TBM) made of Al can give the similar effect but the mass and power consumption of warm-up heater should increase compared to PCM. The amount of PCM can be optimized depending on the component heat dissipation and on/off duty time.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.7
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• pp.1347-1353
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• 2015

We implemented a 10 Gb/s 4-channel vertical cavity surface emission lasers (VCSEL) driver array in a $0.13{\mu}m$ CMOS process technology. To enhance high current resolution, power dissipation, and chip space area, digital APC/AMC with time division sensing technology is primarily adopted. The measured -3 dB frequency bandwidth is 9.2 GHz; the small signal gain is 10.5 dB; the current resolution is 0.01 mA/step, suitable for the wavelength operation up to 10 Gb/s over a wide temperature range. The proposed APC and AMC demonstrate 5 to 20 mA of bias current control and 5 to 20 mA of modulation current control. The whole chip consumes 371 mW of low power under the maximum modulation and bias currents. The active chip size is $3.71{\times}1.3mm^2$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.861-862
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• 2015

In this paper we present a low area 12-bit SAR ADC (Successive Approximation Register Analog-to-Digital Converter). The proposed circuit is fabricated using Magnachip/SK Hynix 1-Poly 6-Metal $0.18-{\mu}m$ CMOS process, and it is powered by a 1.8-V supply. Total chip area is reduced by replacing the MIM capacitors with MOS capacitors instead of the capacitors consisting of overall part in chip area. The proposed circuit showed improved power dissipation of 1.9mW, and chip area of $0.45mm^2$ as compared to conventional research results at the power supply of 1.8V. The designed circuit also showed high SNDR (Signal-to-Noise Distortion Ratio) of 70.51dB, and excellent effective number of bits of 11.4bits.