• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.344-344
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• 2010

A capacitor with engineered tunnel barrier composed of High-k materials has been fabricated. Variable oxide thickness (VARIOT) barrier consisting of thin SiO2/HfO2/Al2O3 (2/1/3 nm) dielectric layers were used as engineered tunneling barrier. We studied the electrical characteristics of multi stacked tunnel layers for various RTA (Rapid Thermal Anneal) and FGA (Forming Gas Anneal) temperature.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.362-365
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• 2002

Hf thin films were deposited on bottom metal using a RF magnetron sputtering method followed by oxidation and annealing in O$_2$ and N$_2$ ambient, respectively. Various top metal electrodes (i.e., Al, Au, and Cu) were deposited by evaporation, and their roles on physical and electrical properties were investigated. Using the XRD, SEM and AFM techniques, we confirmed that the grain size of HfO$_2$ thin films enlarges as a function of oxidation temperature, increasing dielectric constant. However, other electrical properties (e.g., tan) deteriorateas a consequence. The dielectric constant and tan of HfO$_2$ thin films oxidized at 500 $^{\circ}C$ were 17-25 and 3${\times}$10-3 - 2x10-2, respectively, in the frequency range of 1 Hz to 1 MHz. The leakage current density was less than 1${\times}$10-8A/cm2 up to 0.7 MV/cm. In addition, electrical properties of HfO$_2$ thin films (e.g., the dielectric constant, leakage current and tan $\delta$) depend on top metal electrode. We showed that Al top metal electrode results in the best result.

• Transactions on Electrical and Electronic Materials
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• v.15 no.5
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• pp.241-244
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• 2014

Charge trap flash memory capacitors incorporating $(HfO_2)_x(Al_2O_3)_{1-x}$ film, as the charge trapping layer, were fabricated. The effects of the charge trapping layer composition on the memory characteristics were investigated. It is found that the memory window and charge retention performance can be improved by adding Al atoms into pure $HfO_2$; further, the memory capacitor with a $(HfO_2)_{0.9}(Al_2O_3)_{0.1}$ charge trapping layer exhibits optimized memory characteristics even at high temperatures. The results should be attributed to the large band offsets and minimum trap energy levels. Therefore, the $(HfO_2)_{0.9}(Al_2O_3)_{0.1}$ charge trapping layer may be useful in future nonvolatile flash memory device application.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.477-477
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• 2008

For more than three decades, the gate dielectrics in CMOS devices are $SiO_2$ because of its blocking properties of current in insulated gate FET channels. As the dimensions of feature size have been scaled down (width and the thickness is reduced down to 50 urn and 2 urn or less), gate leakage current is increased and reliability of $SiO_2$ is reduced. Many metal oxides such as $TiO_2$, $Ta_2O_4$, $SrTiO_3$, $Al_2O_3$, $HfO_2$ and $ZrO_2$ have been challenged for memory devices. These materials posses relatively high dielectric constant, but $HfO_2$ and $Al_2O_3$ did not provide sufficient advantages over $SiO_2$ or $Si_3N_4$ because of reaction with Si substrate. Recently, $HfO_2$ have been attracted attention because Hf forms the most stable oxide with the highest heat of formation. In addition, Hf can reduce the native oxide layer by creating $HfO_2$. However, new gate oxide candidates must satisfy a standard CMOS process. In order to fabricate high density memories with small feature size, the plasma etch process should be developed by well understanding and optimizing plasma behaviors. Therefore, it is necessary that the etch behavior of $HfO_2$ and plasma parameters are systematically investigated as functions of process parameters including gas mixing ratio, rf power, pressure and temperature to determine the mechanism of plasma induced damage. However, there is few studies on the the etch mechanism and the surface reactions in $BCl_3$ based plasma to etch $HfO_2$ thin films. In this work, the samples of $HfO_2$ were prepared on Si wafer with using atomic layer deposition. In our previous work, the maximum etch rate of $BCl_3$/Ar were obtained 20% $BCl_3$/ 80% Ar. Over 20% $BCl_3$ addition, the etch rate of $HfO_2$ decreased. The etching rate of $HfO_2$ and selectivity of $HfO_2$ to Si were investigated with using in inductively coupled plasma etching system (ICP) and $BCl_3/Cl_2$/Ar plasma. The change of volume densities of radical and atoms were monitored with using optical emission spectroscopy analysis (OES). The variations of components of etched surfaces for $HfO_2$ was investigated with using x-ray photo electron spectroscopy (XPS). In order to investigate the accumulation of etch by products during etch process, the exposed surface of $HfO_2$ in $BCl_3/Cl_2$/Ar plasma was compared with surface of as-doped $HfO_2$ and all the surfaces of samples were examined with field emission scanning electron microscopy and atomic force microscope (AFM).

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.219-219
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• 2010

기존의 플로팅 타입의 메모리는 소자의 소형화에 따른 인접 셀 간의 커플링 현상과 전계에 따른 누설전류의 증가 등과 같은 문제가 발생한다. 이에 대한 해결책으로서 전하 저장 층을 폴리실리콘에서 유전체를 사용하는 SONOS 형태의 메모리와 NFGM (Nano-Floating Gate Memory)연구가 되고 있다. 그러나 높은 구동 전압, 느린 쓰기/지우기 속도 그리고 10년의 전하보존에 대한 리텐션 특성을 만족을 시키지 못하는 문제가 있다. 이러한 문제를 해결 하고자 터널베리어를 엔지니어링 하는 TBM (Tunnel Barrier Engineering Memory) 기술에 대한 연구가 활발히 진행 중이다. TBM 기술은 터널 층을 매우 얇은 다층의 유전체를 사용하여 전계에 따른 터널베리어의 민감도를 증가시킴으로써 빠른 쓰기/지우기 동작이 가능하며, 10년의 전하 보존 특성을 만족 시킬 수 있는 차세대 비휘발성 메모리 기술이다. 또한 고유전율 물질을 터널층으로 이용하면 메모리 특성을 향상 시킬 수가 있다. 일반적으로 TBM 기술에는 VARIOT 구조와 CRESTED 구조로 나눠지는데 본 연구에서는 두 구조의 장점을 가지는 Staggered tunnel barrier 구조를 $Si_3N_4$와 HfAlO을 이용하여 디자인 하였다. 이때 HfO2와 Al2O3의 조성비는 3:1의 조성을 갖는다. $Si_3N_4$와 HfAlO을 각각 3 nm로 적층하여 리세스(Recess) 구조의 트랜지스터를 제작하여 차세대 비휘발성 메모리로써의 가능성을 알아보았다.

• Journal of the Korean institute of surface engineering
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• v.33 no.4
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• pp.251-260
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• 2000

Ta and Hf added Ti-l5Sn-4Nb alloys without V and Al elements for biomaterial were melted by arc furnace in response to recent concerns about the long term safety of Ti-6Al-4V alloy. All specimens were homogenized at $1000^{\circ}C$ and solution treatment was performed at $812^{\circ}C$ and aging treatment at $500^{\circ}C$. The microstructure and mechanical properties were analysed by optical micrograph, hardness tester and instron. Ti-l5Sn-4Nb system alloys showed widmanstatten microstructure which is typical microstructure in $\alpha$＋$\beta$ type Ti alloys. The Ti-l5Sn-4Nb-2Hf and Ti-l5Sn-4Nb-2Ta alloys showed better hardness and tensile strength compared with Ti-6Al-4V. The result of XPS analysis, Ti-l5Sn-4Nb alloy in air atmosphere consisted of $TiO_2$, SnO and NbO.

• Journal of IKEEE
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• v.25 no.1
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• pp.1-9
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• 2021

In this paper, a 4H-SiC UMOSFET was studied which is suitable for high voltage and high current applications. In general, SiO2 is a material most commonly used as a gate dielectric material in SiC MOSFETs. However, since the dielectric constant value is 2.5 times lower than 4H-SiC, it suffers a high electric field and has poor characteristics in the SiO2/SiC junction. Therefore, the static characteristics of a device with high-k material as a gate dielectric and a device with SiO2 were compared using TCAD simulation. The results show BV decreased, VTH decreased, gm increased, and Ron decreased. Especially when the temperature is 300K, the Ron of Al2O3 and HfO2 decreases by 66.29% and 69.49%. and at 600K, Ron decreases by 39.71% and 49.88%, respectively. Thus, Al2O3 and HfO2 are suitable as gate dielectric materials for high voltage SiC MOSFET.

• Journal of the Korean Ceramic Society
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• v.27 no.3
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• pp.369-382
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• 1990

ZrO2-Toughened Alumina-Ceramics(ZTA) with Cr2O3 and HfO2 as addition were synthesized by assintering method for solid solution of Al2O3/Cr2O3 and ZrO2/HfO2, and were prepared by pressureless sintering at 1$600^{\circ}C$. The effects of Cr2O3 and HfO2 on the thermal and mechanical properties, the sintering mechanism, and the wearness between theory and experiment were investigated. Among three kinds of mechanisms such as stress-induced transformation, microcracking, and crack deflection it contributed to the ZTA system with a few exceptons according to composite. We show that wearness can be estimated sufficiently by HV and KIC through theory and experiment.

• Proceedings of the Korean Ceranic Society Conference
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• 2003.04a
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• pp.35.1-35
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• 2003

• Proceedings of the Korean Ceranic Society Conference
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• 2003.04a
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• pp.37.2-37
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• 2003