• 제목/요약/키워드: Heterogeneous Memory

검색결과 71건 처리시간 0.019초

Low-power heterogeneous uncore architecture for future 3D chip-multiprocessors

  • Dorostkar, Aniseh;Asad, Arghavan;Fathy, Mahmood;Jahed-Motlagh, Mohammad Reza;Mohammadi, Farah
    • ETRI Journal
    • /
    • 제40권6호
    • /
    • pp.759-773
    • /
    • 2018
  • Uncore components such as on-chip memory systems and on-chip interconnects consume a large amount of energy in emerging embedded applications. Few studies have focused on next-generation analytical models for future chip-multiprocessors (CMPs) that simultaneously consider the impacts of the power consumption of core and uncore components. In this paper, we propose a convex-optimization approach to design heterogeneous uncore architectures for embedded CMPs. Our convex approach optimizes the number and placement of memory banks with different technologies on the memory layer. In parallel with hybrid memory architecting, optimizing the number and placement of through silicon vias as a viable solution in building three-dimensional (3D) CMPs is another important target of the proposed approach. Experimental results show that the proposed method outperforms 3D CMP designs with hybrid and traditional memory architectures in terms of both energy delay products (EDPs) and performance parameters. The proposed method improves the EDPs by an average of about 43% compared with SRAM design. In addition, it improves the throughput by about 7% compared with dynamic RAM (DRAM) design.

Memory Allocation in Mobile Multitasking Environments with Real-time Constraints

  • Hyokyung, Bahn
    • International Journal of Internet, Broadcasting and Communication
    • /
    • 제15권1호
    • /
    • pp.79-84
    • /
    • 2023
  • Due to the rapid performance improvement of smartphones, multitasking on mobile platforms has become an essential feature. Unlike traditional desktop or server environments, mobile applications are mostly interactive jobs where response time is important, and some applications are classified as real-time jobs with deadlines. When interactive and real-time jobs run concurrently, memory allocation between multitasking applications is a challenging issue as they have different time requirements. In this paper, we study how to allocate memory space when real-time and interactive jobs are simultaneously executed in a smartphone to meet the multitasking requirements between heterogeneous jobs. Specifically, we analyze the memory size required to satisfy the constraints of real-time jobs and present a new model for allocating memory space between heterogeneous multitasking jobs. Trace-driven simulations show that the proposed model provides reasonable performance for interactive jobs while guaranteeing the requirement of real-time jobs.

Evolution of Nonvolatile Resistive Switching Memory Technologies: The Related Influence on Hetrogeneous Nanoarchitectures

  • Eshraghian, Kamran
    • Transactions on Electrical and Electronic Materials
    • /
    • 제11권6호
    • /
    • pp.243-248
    • /
    • 2010
  • The emergence of different and disparate materials together with the convergence of both the 'old' and 'emerging' technologies is paving the way for integration of heterogeneous technologies that are likely to extend the limitations of silicon technology beyond the roadmap envisaged for complementary metal-oxide semiconductor. Formulation of new information processing concepts based on novel aspects of nano-scale based materials is the catalyst for new nanoarchitectures driven by a different perspective in realization of novel logic devices. The memory technology has been the pace setter for silicon scaling and thus far has pave the way for new architectures. This paper provides an overview of the inevitability of heterogeneous integration of technologies that are in their infancy through initiatives of material physicists, computational chemists, and bioengineers and explores the options in the spectrum of novel non-volatile memory technologies considered as forerunner of new logic devices.

에너지 및 성능 효율적인 이종 모바일 저장 장치용 동적 부하 분산 (Energy and Performance-Efficient Dynamic Load Distribution for Mobile Heterogeneous Storage Devices)

  • 김영진;김지홍
    • 한국컴퓨터정보학회논문지
    • /
    • 제14권4호
    • /
    • pp.9-17
    • /
    • 2009
  • 본 논문에서는 운영체제 수준에서 에너지 절감과 함께 I/O 성능 개선을 목적으로 하여 소형 하드 디스크와 플래시 메모리를 이종의 저장 장치로 가지는 모바일 시스템에 대해 동적 부하 분산 기법을 제안한다. 제안 기법은 부하가 에너지 및 성능 효율적인 방법으로 하드디스크와 플래시 메모리의 이종성의 저장 장치 구성에 대해서 어떻게 효율적으로 분산될 수 있을 것인지를 발견하기 위하여 파일 배치 기법과 버퍼 캐시 관리 기법을 결합하는 접근법을 취한다. 제안한 기법은 폭넓은 시뮬레이션을 통해서 기존의 기법들과 비교하여 이종의 모바일 저장장치들에 대해서 더 개선된 실험 결과를 보이는 것으로 나타났다.

Stationary bootstrapping for structural break tests for a heterogeneous autoregressive model

  • Hwang, Eunju;Shin, Dong Wan
    • Communications for Statistical Applications and Methods
    • /
    • 제24권4호
    • /
    • pp.367-382
    • /
    • 2017
  • We consider an infinite-order long-memory heterogeneous autoregressive (HAR) model, which is motivated by a long-memory property of realized volatilities (RVs), as an extension of the finite order HAR-RV model. We develop bootstrap tests for structural mean or variance changes in the infinite-order HAR model via stationary bootstrapping. A functional central limit theorem is proved for stationary bootstrap sample, which enables us to develop stationary bootstrap cumulative sum (CUSUM) tests: a bootstrap test for mean break and a bootstrap test for variance break. Consistencies of the bootstrap null distributions of the CUSUM tests are proved. Consistencies of the bootstrap CUSUM tests are also proved under alternative hypotheses of mean or variance changes. A Monte-Carlo simulation shows that stationary bootstrapping improves the sizes of existing tests.

이종 모바일 멀티태스킹 환경을 위한 실시간 작업 인지형 메모리 할당 기술 연구 (Real-time Task Aware Memory Allocation Techniques for Heterogeneous Mobile Multitasking Environments)

  • 반효경
    • 한국인터넷방송통신학회논문지
    • /
    • 제22권3호
    • /
    • pp.43-48
    • /
    • 2022
  • 최근 스마트폰의 성능이 급격히 향상되고 모바일 플랫폼에서 백그라운드 앱의 실행이 늘면서 모바일 환경의 멀티태스킹이 활성화되고 있다. 모바일 환경에서는 종래의 데스크탑 및 서버 응용들과 달리 응답시간이 중요한 대화형 작업들이 대부분을 차지하고 있으며, 일부 응용은 데드라인이 존재하는 실시간 작업에 해당된다. 본 논문에서는 스마트폰에서 실시간 작업과 대화형 작업이 동시에 실행될 때 메모리 관리를 어떻게 함으로써 이질적인 멀티태스킹 환경의 요구사항을 충족할 수 있는지에 대해 연구한다. 본 논문에서는 실시간 작업의 요구 조건 만족을 위해 필요한 메모리 크기를 분석 및 모델링하고 이에 기반해서 멀티태스킹 작업 간의 메모리를 할당하는 방안을 제안한다. 이종 앱의 스토리지 접근 트레이스를 추출하고 이에 기반한 시뮬레이션을 통해 제안한 기법이 실시간 작업의 요구를 일정 수준으로 보장하면서 대화형 작업에 합리적인 성능을 제공함을 확인하였다.

3-D Hetero-Integration Technologies for Multifunctional Convergence Systems

  • 이강욱
    • 마이크로전자및패키징학회지
    • /
    • 제22권2호
    • /
    • pp.11-19
    • /
    • 2015
  • Since CMOS device scaling has stalled, three-dimensional (3-D) integration allows extending Moore's law to ever high density, higher functionality, higher performance, and more diversed materials and devices to be integrated with lower cost. 3-D integration has many benefits such as increased multi-functionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging volume, because it vertically stacks multiple materials, technologies, and functional components such as processor, memory, sensors, logic, analog, and power ICs into one stacked chip. Anticipated applications start with memory, handheld devices, and high-performance computers and especially extend to multifunctional convengence systems such as cloud networking for internet of things, exascale computing for big data server, electrical vehicle system for future automotive, radioactivity safety system, energy harvesting system and, wireless implantable medical system by flexible heterogeneous integrations involving CMOS, MEMS, sensors and photonic circuits. However, heterogeneous integration of different functional devices has many technical challenges owing to various types of size, thickness, and substrate of different functional devices, because they were fabricated by different technologies. This paper describes new 3-D heterogeneous integration technologies of chip self-assembling stacking and 3-D heterogeneous opto-electronics integration, backside TSV fabrication developed by Tohoku University for multifunctional convergence systems. The paper introduce a high speed sensing, highly parallel processing image sensor system comprising a 3-D stacked image sensor with extremely fast signal sensing and processing speed and a 3-D stacked microprocessor with a self-test and self-repair function for autonomous driving assist fabricated by 3-D heterogeneous integration technologies.

CPU-GPU간 긴밀성을 위한 효율적인 공유메모리 접근 방법과 검증 시스템 구현 (Implementation of Integrated CPU-GPU for Efficient Uniform Memory Access Method and Verification System)

  • 박현문;권진산;황태호;김동순
    • 대한임베디드공학회논문지
    • /
    • 제11권2호
    • /
    • pp.57-65
    • /
    • 2016
  • In this paper, we propose a system for efficient use of shared memory between CPU and GPU. The system, called Fusion Architecture, assures consistency of the shared memory and minimizes cache misses that frequently occurs on Heterogeneous System Architecture or Unified Virtual Memory based systems. It also maximizes the performance for memory intensive jobs by efficient allocation of GPU cores. To test between architectures on various scenarios, we introduce the Fusion Architecture Analyzer, which compares OpenMP, OpenCL, CUDA, and the proposed architecture in terms of memory overhead and process time. As a result, Proposed fusion architectures show that the Fusion Architecture runs benchmarks 55% faster and reduces memory overheads by 220% in average.

오토인코더를 이용한 요인 강화 HAR 모형 (Autoencoder factor augmented heterogeneous autoregressive model)

  • 박민수;백창룡
    • 응용통계연구
    • /
    • 제35권1호
    • /
    • pp.49-62
    • /
    • 2022
  • 실현 변동성은 강한 종속성을 가짐이 잘 알려져 있으며, 글로벌 금융 시장과 유기적으로 연관이 되어 있을 뿐만 아니라 환율, 유가, 이자율 등의 거시적인 지표와도 밀접한 관계가 있다. 본 논문은 이러한 실현 변동성의 효과적인 예측을 위해서 오토인코더를 이용한 FAHAR (autoencoder factor-augmented heterogeneous autoregressive, AE-FAHAR) 모형을 제안한다. AE-FAHAR 모형은 강한 종속성을 HAR 구조로 반영하고, 외부 효과에 대한 영향을 오토인코더를 사용하여 몇 개의 요인으로 추출하여 이를 반영한다. 오토인코더는 비선형 방법으로 요인을 추정하기에 많은 계산 시간이 필요하지만 복잡하고 비정상성을 가질 수 있는 고차원 시계열 자료의 요약에 더 적합하다. 이는 곧 실증 자료 분석을 통해 AE-FAHAR 모형이 예측 오차를 줄임을 확인할 수 있었다. 또한 계산 시간을 줄이고 추정 오차를 줄이기 위해 오토인코더에 사전학습 및 앙상블을 적용하는 등의 방법에 대해서도 논의하였다.

TP-Sim: 트레이스 기반의 프로세싱 인 메모리 시뮬레이터 (TP-Sim: A Trace-driven Processing-in-Memory Simulator)

  • 김정근
    • 반도체디스플레이기술학회지
    • /
    • 제22권3호
    • /
    • pp.78-83
    • /
    • 2023
  • This paper proposes a lightweight trace-driven Processing-In-Memory (PIM) simulator, TP-Sim. TP-Sim is a General Purpose PIM (GP-PIM) simulator that evaluates various PIM system performance-related metrics. Based on instruction and memory traces extracted from the Intel Pin tool, TP-Sim can replay trace files for multiple models of PIM architectures to compare its performance. To verify the availability of TP-Sim, we estimated three different system configurations on the STREAM benchmark. Compared to the traditional Host CPU-only systems with conventional memory hierarchy, simple GP-PIM architecture achieved better performance; even the Host CPU has the same number of in-order cores. For further study, we also extend TP-Sim as a part of a heterogeneous system simulator that contains CPU, GPGPU, and PIM as its primary and co-processors.

  • PDF