• Journal of IKEEE
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• v.18 no.4
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• pp.447-455
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• 2014

In this research, n-based 4H-MOS Capacitor was fabricated with PECVD (plasma enhanced chemical vapor deposition) process for improving SiC/$SiO_2$ interface properties known as main problem of 4H-SiC MOSFET. To overcome the problems of dry oxidation process such as lower growth rate, high interface trap density and low critical electric field of $SiO_2$, PECVD and NO annealing processes are used to MOS Capacitor fabrication. After fabrication, MOS Capacitor's interface properties were measured and evaluated by hi-lo C-V measure, I-V measure and SIMS. As a result of comparing the interface properties with the dry oxidation case, improved interface and oxide properties such as 20% reduced flatband voltage shift, 25% reduced effective oxide charge density, increased oxide breakdown field of 8MV/cm and best effective barrier height of 1.57eV, 69.05% reduced interface trap density in the range of 0.375~0.495eV under the conduction band are observed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.3 no.1
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• pp.229-234
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• 1999

We analyzed the reliability characteristics in platinum schottky diodes with variations of n-type silicon substrates concentrations and temperature variations of measurements. The parameters of reliability measurement analysis are saturation current. turn-on voltage and ideality factor in the forward bias, the breakdown voltage in the reverse bias with device shapes. The shape of devices are square type and long rectangular type for edge effect. As a result, we analyzed that the forward turn-on voltage, barrier height, dynamic resistance and reverse breakdown voltage were decreased but ideality factor and saturation current were increased by increased concentration in platinum and n-silicon junction parts. In measurement temperature(RT, $50^{\circ}C$, $75^{\circ}C$), the extracted electrical parameter values of reliability characteristics were increased at the higher temperature under the forward and reverse bias. The long rectangular type devices were more decreased than the square type in reverse breakdown voltage by tunneling effects of edge part.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.1
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• pp.48-56
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• 1998

Pr\ulcornerO\ulcorner-based ZnO varistors were fabricated in the range of $Y_2$O$_3$additive content from 0.5 to 4.0mol%, and its microstructure and electrical properties were investigated. Yttrium was distributed nearly in the grain boundaries and the cluster phase formed at nodal point but more in cluster phase. The average grain size was decreased markedly from 34.9 to 8.6${\mu}{\textrm}{m}$ with increasing $Y_2$O$_3$additive content. It is believed that the decrease of grain size is attributed to the formation of cluster phase and the weakening of driving force for liquid sintering. As a result, $Y_2$O$_3$was acted as the inhibitor of the grain growth. With increasing $Y_2$O$_3$additive content, the varistor voltage, the activation energy, and the nonlinear exponent increased whereas the leakage current decreased, especially 4.0mol% $Y_2$O$_3$-added varistor exhibited very good I-V characteristics; nonlinear exponent 87.42 and leakage current 46.77nA. On the other hand, as $Y_2$O$_3$additive content increases, the varistor showed tendency of the salient decrease for donor concentration and the increase for barrier height. Conclusively, it is estimated that ZnO:Pr varistor compositions added more than 2.0mol% $Y_2$O$_3$are to be used to fabricate useful varistors.

• Electrical & Electronic Materials
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• v.8 no.5
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• pp.619-625
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• 1995

Polycrystalline CdTe thin film has been studied for photovoltaic application due to the 1.45 eV band gap energy ideal for solar energy conversion and high absorption coefficient. The formation of low resistance contact to p-CdTe is difficult because of large work function(>5.5eV). Common methods for ohmic contact to p-CdTe are to form a p+ region under the contact by in-diffusion of contact material to reduce the barrier height and modify a p-CdTe surface layer using chemical treatment. In this study, the surface chemical treatment of p CdTe was carried out by H$\_$3/PO$\_$4/+HNO$\_$3/ or K$\_$2/Cr$\_$2/O$\_$7/+H$\_$2/SO$\_$4/ solution to provide a Te-rich surface. And various thin film contact materials such as Cu, Au, and Cu/Au were deposited by E-beam evaporation to form ohmic contact to p-CdTe. After the metallization, post annealing was performed by oven heat treatment at 150.deg. C or by RTA(Rapid Thermal Annealing) at 250-350.deg. C. Surface chemical treatments of p-CdTe thin film improved metal/p-CdTe interface properties and post heat treatment resulted in low contact resistivity to p-CdTe.Of the various contact metal, Cu/Au and Cu show low contact resistance after oven and RTA post-heat treatments, respectively.

• Journal of Korean Society of Coastal and Ocean Engineers
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• v.11 no.4
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• pp.189-196
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• 1999

In order to verify a numerical model for the calculation of wave motion around an offshore barrier in shallow water, laboratory physical experiments are necessary. In this study, sample experiments are carried out on the wave and wave induced current fields due to a sloping bottom topography and on that due to an isolated structure from the coastline. The water body is divided into 4 levels, in which the current tracking floaters are deployed to measure the wave induced currents. Data measurement was continued using the limited wave gauges and current tracking floaters including a video camera from the top. The wave heights for the preselected surface and time-averaged velocity distributions at each level were measured in detail. The distribution of wave and current fields was analyzed precisely combining the whole measured laboratory data. Moreover, comprehensive analyses were carried out on non-linearity of wave transformation in terms of skewness and atiltness.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.4
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• pp.45-50
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• 2006

Copper via filling is the important factor in 3-D stacking interconnection of SiP (system in package). As the packaging density is getting higher, the size of via is getting smaller. When DC electroplating is applied, a defect-free hole cannot be obtained in a small size via hole. To prevent the defects in holes, pulse and pulse reverse current was applied in copper via filling. The holes, $20\and\;50{\mu}m$ in diameter and $100{\sim}190\;{\mu}m$ in height. The holes were prepared by DRIE method. Ta was sputtered for copper diffusion barrier followed by copper seed layer IMP sputtering. Via specimen were filled by DC, pulse and pulse-reverse current electroplating methods. The effects of additives and current types on copper deposits were investigated. Vertical and horizontal cross section of via were observed by SEM to find the defects in via. When pulse-reverse electroplating method was used, defect free via were successfully obtained.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.2 s.35
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• pp.129-134
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• 2005

Electroplating copper is the important role in formation of 3D stacking interconnection in SiP (System in Package). The I-V characteristics curves are investigated at different electrolyte conditions. Inhibitor and accelerator are used simultaneously to investigate the effects of additives. Three different sizes of via are tested. All via were prepared with RIE (reactive ion etching) method. Via's diameter are 50, 75, $100{\mu}m$ and the height is $100{\mu}m$. Inside via, Ta was deposited for diffusion barrier and Cu was deposited fer seed layer using magnetron sputtering method. DC, pulse and pulse revere current are used in this study. With DC, via cannot be filled without defects. Pulse plating can improve the filling patterns however it cannot completely filled copper without defects. Via was filled completely without defects using pulse-reverse electroplating method.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.8
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• pp.738-748
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• 2008

In this study, it has been investigated on the changing behavior of electrical properties in $ZnO-Bi_2O_3-Sb_2O_3$ (Sb/Bi=2.0, 1.0 and 0.5) ceramics. The samples were prepared by conventional ceramic process, and then characterized by I-V, C-V curve plots, impedance and modulus spectroscopy (IS & MS) measurement. The electrical properties of ZBS systems were strongly dependent on Sb/Bi. In ZBS systems, the varistor characteristics were deteriorated noticeably with increasing Sb/Bi and the donor density and interface state density were increased with increasing Sb/Bi. On the other hand, we observed that the grain boundary reacted actively with the ambient oxygen according to Sb/Bi ratio. Especially the grain boundaries of Sb/Bi=0.5 systems were divided into two types, i.e. sensitive to oxygen and thus electrically active one and electrically inactive intergranular one with temperature. Besides, the increased pyrochlore and $\beta$-spinel phase with Sb/Bi ratio caused the distributional inhomogeneity in the grain boundary barrier height and the temperature instability. To the contrary, the grain boundary layer was relatively homogeneous and more stable to temperature change and kept the system highly nonlinear at high Bi-rich phase contents.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.310-313
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• 2000

In this study, the Au/Ni and Au/Ni/Si/Ni layers prepared by electron beam evaporation were used to form ohmic contacts on p-type GaN. Before rapid thermal annealing, the current-voltage(I-V) characteristic of Au/Ni and Au/Ni/Si/Ni contact on p-type GaN film shows non-ohmic behavior. A Specific contact resistance as 3.4$\times$10$^{-4}$ Ω-$\textrm{cm}^2$ was obtained after 45$0^{\circ}C$-RTA. The Schottky barrier height reduction may be attributed to the presence of Ga-Ni and Ga-Au compounds, such as Ga$_4$Ni$_3$, Ga$_4$Ni$_3$, and GaAu$_2$ at the metal - semiconductor interface. The mixing behaviors of both Ni and Au have been studied by using X-ray photoelectron spectroscopy. In addition, X-ray diffraction measurements indicate that the Ni$_3$N, NiGa$_4$, Ni$_2$Si, and Ni$_3$Si$_2$ Compounds were formed at the metal-semiconductor interface.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.150-150
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• 2008

본 연구에서는 Wet chemistry damage가 Nanopatterned p-ohmic electrode에 미치는 영향을 연구하였다. Nanopattern은 Metal clustering을 이용하여, P-GaN와 Ohmic형성에 유리한 Pd을 50$\AA$ 적층한 후 Rapid Thermal Annealing방법으로 $850^{\circ}C$, $N_2$분위기에서 3min열처리를 하여 Pd Clustering mask 를 제작하였다. Wet etching은 $85^{\circ}C$, $H_3PO_4$조건에서 시간에 따라 Sample을 Dipping하는 방법으로 시행하였다 Ohmic test를 위해서 Circular - Transmission line Model 방법을 이용하였으며, Atomic Force Microscopy과 Parameter Analyzer로 Nanopatterned GaN surface위에 형성된 Ni/ Au Contact에서의 전기적 분석과, 표면구조분석을 시행하였다. AFM결과 Wet처리시간에 따라서 Etching형상 및 Etch rate이 영향을 받는 것이 확인되었고, Ohmic test에서 Wet chemistry처리에 의한 Tunneling parameter와 Schottky Barrier Height가 크게 증/감함을 관찰하였다. 이러한 결과들은 Wet처리에 의해서 발생된 Defect가 GaN의 표면과 하부에서 발생되며, Deep acceptor trap 및 transfer거동과 밀접한 관련이 있음을 확인 할 수 있었다. 보다 자세한 Transport 및 Wet chemical처리영향에 관한 형성 Mechanism은 후에 I-V-T, I-V, C-V, AFM결과 들을 활용하여 발표할 예정이다.