• Title/Summary/Keyword: Hardware simulator

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Multi-Programmed Simulation of a Shared Memory Multiprocessor System (공유메모리 다중프로세서 시스템의 다중 프로그래밍 모의실험 기법)

  • 최효진;전주식
    • Journal of KIISE:Computer Systems and Theory
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    • v.30 no.3_4
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    • pp.194-204
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    • 2003
  • The performance of a shared memory multiprocessor system is dependent on the system software such as scheduling policy as well as hardware system. Most of existing simulators, however, do not support simulation for multi-programmed environment because they can execute only a single benchmark application at a time. We propose a multi-programmed simulation method on a program-driven simulator, which enables the concurrent executions of multiple parallel workloads contending for limited system resources. Using the proposed method, system developers can measure and analyze detailed effects of resource conflicts among the concurrent applications as well as the effects of scheduling policies on a program-driven simulator. As a result, the proposed multi-programmed simulation provides more accurate and realistic performance projection to design a multiprocessor system.

Development and Evaluation of Smart Secondary Controls Using iPad for People with Hemiplegic Disabilities

  • Song, Jeongheon;Kim, Yongchul
    • Journal of the Ergonomics Society of Korea
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    • v.34 no.2
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    • pp.85-101
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    • 2015
  • Objective: The purpose of this study was to develop and evaluate smart secondary controls using iPad for the drivers with physical disabilities in the driving simulator. Background: The physically disabled drivers face problems in the operation of secondary control devices that accept a control input from a driver for the purpose of operating the subsystems of a motor vehicle. Many of conventional secondary controls consist of small knobs or switches that physically disabled drivers have difficulties in grasping, pulling or twisting. Therefore, their use while driving might increase distraction and workload because of longer operation time. Method: We examined the operation time of conventional and smart secondary controls, such as hazard warning, turn signal, window, windshield wiper, headlights, automatic transmission and horn. The hardware of smart secondary control system was composed of iPad, wireless router, digital input/output module and relay switch. We used the STISim Drive3 software for driving test, customized Labview and Xcode programs for interface control of smart secondary system. Nine subjects were involved in the study for measuring operation time of secondary controls. Results: When the driver was in the stationary condition, the average operation time of smart secondary devices decreased 32.5% in the normal subjects (p <0.01), 47.4% in the subjects with left hemiplegic disabilities (p <0.01) and 38.8% in the subjects with right hemiplegic disabilities (p <0.01) compared with conventional secondary devices. When the driver was driving for the test in the simulator, the average operation time of smart secondary devices decreased 36.1% in the normal subjects (p <0.01), 41.7% in the subjects with left hemiplegic disabilities (p <0.01) and 34.1% in the subjects with right hemiplegic disabilities (p <0.01) compared with conventional secondary devices. Conclusion: The smart secondary devices using iPad for people with hemiplegic disabilities showed significant reduction of operation time compared with conventional secondary controls. Application: This study can be used to design secondary controls for adaptive vehicles and to improve the quality of life of the people with disabilities.

Study on Chip Design & Implementation of 32 Bit Floating Point Compatible DSP (32비트 부동소수점 호환 DSP의 설계 및 칩 구현에 관한 연구)

  • Woo, Jong-Sik;Seo, Jin-Keun;Lim, Jae-Young;Park, Ju-Sung
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.37 no.11
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    • pp.74-84
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    • 2000
  • This paper deals with procedures for design and implementation of a DSP, which is compatible with TMS320C30 DSP. CBS(Cycle Based Simulator) is developed to study the architecture of the target DSP. The simulator gives us detailed information such as function block operation, control signal values, register condition, bus and memory values when a instruction is being carried out. RTL design is carried out by VHDL. Logic simulation and hardware emulation are employed to verify proper operation of the design. The DSP is fabricated with 0.6${\mu}m$ CMOS technology. The Chip has 450,000 gates complexity, $9{\times}9mm^2$ area, 20 MIPS operation speed. It is confirmed by running 109 instructions out of 114 instructions and 13 kinds of algorithm that the developed DSP has compatibility with TMS320C30.

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Development ERC32 Processor Emulator based on QEMU (QEMU를 기반으로 한 ERC32 프로세서 에뮬레이터 개발)

  • Choi, Jong-Wook;Shin, Hyun-Kyu;Lee, Jae-Seung;Cheon, Yee-Jin
    • Aerospace Engineering and Technology
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    • v.10 no.2
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    • pp.105-113
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    • 2011
  • During the development of flight software, the processor emulator and satellite simulator are essential tools for software development and verification, which can be substituted for the actual hardware. LEO satellites being developed by KARI recently use the MCM-ERC32SC processor for on-board computer (OBC). For the flight software (FSW) development and testing, the software-based spacecraft simulator was developed using TSIM-ERC32 processor emulator from Aeroflex Gaisler. It is needed to get rid of the constraints and dependencies of TSIM-ERC32 processor emulator and to obtain high performance processor emulator to develop full satellite simulator. This paper presents the development of the ERC32 emulator based on open source dynamic translator, QEMU, as the first step. And it describes the software development and testing/debugging on the developed emulator.

High Resolution Radar Model to Simulate Detection/Tracking Performance of Multi-Function Radar in War Game Simulator (통합 교전 시뮬레이터 환경에서 다기능 레이다 탐지/추적 성능 모의를 위한 고해상도 레이다 모델)

  • Rim, Jae-Won;Oh, Suhyun;Koh, Il-Suek
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.30 no.1
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    • pp.70-78
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    • 2019
  • In this paper, modeling of a high-resolution multi-function radar is proposed to simulate radar performance in a war game simulator, called AddSIM. To incorporate the multi-function radar model into the AddSIM, the modeling must comprise a component-based structure consisting of physics, logics, and information blocks. Therefore, we assign the RF hardware of a RADAR as the physic block, a controller as the logics block, and the RF specifications of the RADAR as the information block. Detailed modeling of the physics and logics blocks are addressed, and data structure is also presented on an engineering level. On a multi-target engaged scenario, the performance of the multi-function radar is numerically analyzed and its validation is examined.

Performance analysis and verification of underwater acoustic communication simulator in medium long-range multiuser environment (중장거리 다중송신채널 환경에서 수중음향통신 시뮬레이터 성능 분석 및 검증)

  • Park, Heejin;Kim, Donghyeon;Kim, J.S.;Song, Hee-Chun;Hahn, Joo Young
    • The Journal of the Acoustical Society of Korea
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    • v.37 no.6
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    • pp.451-456
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    • 2018
  • UAComm (Underwater Acoustic Communication) is an active research area, and many experiment has been performed to develop UAComm system. In this paper, we investigate the possibility of modifying and applying VirTEX (Virtual Time series EXperiment) to medium long range MIMO (Multiple-Input Multiple-Output) UAComm of about 20 km range for the analysis and performance prediction of UAComm system. Since VirTEX is a time-domain simulator, the generated time series can be used in HILS (Hardware In the Loop Simulation) to develop UAComm system. The developed package is verified through comparing with the sea-going FAF05 (Focused Acoustic Field 2005) experimental data. The developed simulator can be used to predict the performance of UAComm system, and even replace the expensive sea-going experiment.

Symbol Synchronization Technique using Bit Decision Window for Non-Coherent IR-UWB Systems (Bit Decision 윈도우를 이용한 Noncoherent IR-UWB 수신기의 심벌 동기에 관한 연구)

  • Lee, Soon-Woo;Park, Young-Jin;Kim, Kwan-Ho
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.44 no.2
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    • pp.15-21
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    • 2007
  • In this paper, we propose a technique of a practical symbol acquisition and tracking using a low complex ADC and simple digital circuits for noncoherent asynchronous impulse-radio-based Ultra Wideband (IR-UWB) receiver based on energy detection. Compared to previous approaches of detecting an exact acquisition time that require much hardware resource, the proposed technique is to detect the target symbol by finding the symbol acquisition interval per symbol with a target symbo, thus the complexity of the complete signal processing and power consumption by ADC are reduced. To do this, we define the bit decision window (BDW) and analyze the relation between SNR, hardware resource, size of BDW and BER(Bit Error Rate). Using the results, the optimum BDW size for the minimum BER with limited hardware resource is selected. The proposed synchronization technique is verified with an aid of a simulator programmed by considering practical impulse channels.

Development of HIL simulator for performance validation of stack inlet gases temperature controller of marine solid oxide fuel cell system (선박용 고체산화물형 연료전지 시스템의 스택 공급 가스 온도 제어기 성능 검증을 위한 HIL 시뮬레이터 개발)

  • Ahn, Jong-Woo;Park, Sang-Kyun
    • Journal of Advanced Marine Engineering and Technology
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    • v.37 no.6
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    • pp.582-588
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    • 2013
  • Solid Oxide Fuel Cell (SOFC) has been focused as a promising power source, which can replace a diesel engine regarding as major source of air pollution by the ship, due to high efficiency and eco-friendly. High operating temperature of SOFC is enable to secure of high efficiency, use various fuels and no need of high priced catalyst, but it may damage to components of SOFC. Therefore temperature control system has to be designed and validated before employing the fuel cell system for securing high efficiency and reliability. In this paper, instead of using typical method to validate performance of the controller, which consumes high cost and time, performance validation system using Hardware-in-the-loop simulation was developed and validated performence of the designed temperature controller for SOFC system.

DEVELOPMENT AND IMPLEMENTATION OF DISTRIBUTED HARDWARE-IN-THE-LOOP SIMULATOR FOR AUTOMOTIVE ENGINE CONTROL SYSTEMS

  • YOON M.;LEE W.;SUNWOO M.
    • International Journal of Automotive Technology
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    • v.6 no.2
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    • pp.107-117
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    • 2005
  • A distributed hardware-in-the-loop simulation (HILS) platform is developed for designing an automotive engine control system. The HILS equipment consists of a widely used PC and commercial-off-the-shelf (COTS) I/O boards instead of a powerful computing system and custom-made I/O boards. The distributed structure of the HILS system supplements the lack of computing power. These features make the HILS equipment more cost-effective and flexible. The HILS uses an automatic code generation extension, REAL-TIME WORKSHOP$^{ (RTW$^{) of MATLAB$^{ tool-chain and RT-LAB$^{, which enables distributed simulation as well as the detection and generation of digital event between simulation time steps. The mean value engine model, which is used in control design phase, is imported into this HILS. The engine model is supplemented with some I/O subsystems and I/O boards to interface actual input and output signals in real-time. The I/O subsystems are designed to imitate real sensor signals with high fidelity as well as to convert the raw data of the I/O boards to the appropriate forms for proper interfaces. A lot of attention is paid to the generation of a precise crank/ earn signal which has the problem of quantization in a conventional fixed time step simulation. The detection of injection! command signal which occurs between simulation time steps are also successfully compensated. In order to prove the feasibility of the proposed environment, a simple PI controller for an air-to-fuel ratio (AFR) control is used. The proposed HILS environment and I/O systems are shown to be an efficient tool to develop various control functions and to validate the software and hardware of the engine control system.

Design of Optimized ARIA Crypto-Processor Using Composite Field S-Box (합성체 S-Box 기반 최적의 ARIA 암호프로세서 설계)

  • Kang, Min Sup
    • KIPS Transactions on Computer and Communication Systems
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    • v.8 no.11
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    • pp.271-276
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    • 2019
  • Conventional ARIA algorithm which is used LUT based-S-Box is fast the processing speed. However, the algorithm is hard to applied to small portable devices. This paper proposes the hardware design of optimized ARIA crypto-processor based on the modified composite field S-Box in order to decrease its hardware area. The Key scheduling in ARIA algorithm, both diffusion and substitution layers are repeatedly used in each round function. In this approach, an advanced key scheduling method is also presented of which two functions are merged into only one function for reducing hardware overhead in scheduling process. The designed ARIA crypto-processor is described in Verilog-HDL, and then a logic synthesis is also performed by using Xilinx ISE 14.7 tool with target the Xilnx FPGA XC3S1500 device. In order to verify the function of the crypto-processor, both logic and timing simulation are also performed by using simulator called ModelSim 10.4a.