• Journal of KIISE:Computer Systems and Theory
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• v.26 no.7
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• pp.752-765
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• 1999

대부분 병렬처리 시스템에서 성능 파라미터는 복잡하고 프로그램의 수행 시 예견할 수 없게 변하기 때문에 컴파일러가 프로그램 수행에 대한 최적의 성능 파라미터들을 컴파일 시에 결정하기가 힘들다. 본 논문은 병렬 처리 시스템의 프로그램 수행 시, 변화하는 시스템 성능 상태에 따라 전체 성능이 최적화로 적응하는 적응 수행 방식을 제안한다. 본 논문에서는 이 적응 수행 방식 중에 적응 프로그램 수행을 위한 이론적인 방법론 및 구현 방법에 대해 제안하고 적응 제어 수행을 위해 프로그램의 데이타 공유 단위에 대한 적응방식(적응 입도 방식)을 사용한다. 적응 프로그램 수행 방식은 프로그램 수행 시 하드웨어와 컴파일러의 도움으로 프로그램 자신이 최적의 성능을 얻을 수 있도록 적응하는 방식이다. 적응 제어 수행을 위해 수행 시에 병렬 분산 공유 메모리 시스템에서 프로세서 간 공유될 수 있은 데이타의 공유 상태에 따라 공유 데이타의 크기를 변화시키는 적응 입도 방식을 적용했다. 적응 입도 방식은 기존의 공유 메모리 시스템의 공유 데이타 단위의 통신 방식에 대단위 데이타의 전송 방식을 사용자의 입장에 투명하게 통합한 방식이다. 시뮬레이션 결과에 의하면 적응 입도 방식에 의해서 하드웨어 분산 공유 메모리 시스템보다 43%까지 성능이 개선되었다. Abstract On parallel machines, in which performance parameters change dynamically in complex and unpredictable ways, it is difficult for compilers to predict the optimal values of the parameters at compile time. Furthermore, these optimal values may change as the program executes. This paper addresses this problem by proposing adaptive execution that makes the program or control execution adapt in response to changes in machine conditions. Adaptive program execution makes it possible for programs to adapt themselves through the collaboration of the hardware and the compiler. For adaptive control execution, we applied the adaptive scheme to the granularity of sharing adaptive granularity. Adaptive granularity is a communication scheme that effectively and transparently integrates bulk transfer into the shared memory paradigm, with a varying granularity depending on the sharing behavior. Simulation results show that adaptive granularity improves performance up to 43% over the hardware implementation of distributed shared memory systems.

• Journal of Advanced Navigation Technology
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• v.14 no.3
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• pp.328-335
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• 2010

In this paper, an efficient algorithm and area-efficient hardware architecture have been proposed for $2{\times}2$ MIMO-OFDM based WLAN baseband modem with two transmit and two receive antennas. To enhance the performance of the receiver, the efficient timing synchronization algorithm and symbol detector based on MML algorithm are presented. Also, by sharing the hardware block with multi-stage pipeline structure and using the complex multiplier based on polar-coordinate, the complexity of the proposed architecture is dramatically decreased. The proposed area-efficient hardware design was designed in hardware description language (HDL) and synthesized to gate-level circuits using 0.13um CMOS standard cell library. As a result, the complexity of the proposed modem receiver is reduced by 56% over the conventional architecture.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.9
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• pp.86-94
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• 1998

This paper proposes a new fast block-matching algorithm, named MFSS(Modified Four-Step Search) algorithm, which has better performance and is more adequate for hardware realization than the existing fast algorithms. The proposed algorithm is suitable for hardware realization since it has a unique regularity during the search procedure. It is shown from simulation results that its performance is close to that of FS(Full Search) algorithm. This paper also proposes a VLSI architecture and presents some design results of a motion estimator and compensator which adopted the MFSS algorithm. The important aspects considered in designing a motion estimator and compensator are hardware complexity of design results, and total delay needed to generate the motion compensated data after finding the motion vectors. Hardware complexity is minimized by using just nine PE(Process Element)'s, and total delay is minimized by sharing search memory of the motion estimator and compensator.

• The Journal of the Korea Contents Association
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• v.12 no.5
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• pp.40-51
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• 2012

In this paper, we design and implement a SNS-web platform based video seminar system which supports effective information sharing and cooperation. The proposed system has 3 characteristics. First, a user can take part in Web-based video seminar without installing a specific hardware or software because our system has been developed with Java Web Start. Secondly, our system can be executed on various operating systems and internet web browsers. Thirdly, our system can support the expert knowledge sharing and cooperation among experts who are connected on SNS because the system operate on SNS-web platform. Finally, we show from our performance analysis that our system is efficient in terms of average delay time.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.297-299
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• 2016

In this paper, Power Generator modeling for LNG ship has been performed and monitoring system has been developed in MATLAB/SIMULINK. The principal component of Power Generator are engine part(Diesel Engine, Turbine Engine) which provides the mechanical power and synchronous generator which convert the mechanical power into electrical power. Also, load sharing between paralleled generators has been performed to share a total load that exceeds the capacity of a single generator and designated ship lumped load simulations have been carried out. A validity of these systems has been verified by comparison between simulation results and estimated result from the designated lumped load.

• Journal of the Korea Society of Computer and Information
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• v.22 no.9
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• pp.91-97
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• 2017

IoT (Internet of Things) systems are based on heterogeneous hardware systems of different types of devices interconnected each other, ranging from miniaturized and low-power wireless sensor node to cloud servers. These IoT systems composed of heterogeneous hardware utilize data sets collected from a particular set of sensors or control designated actuators when needed using open APIs created through abstraction of devices' resources associated to service applications. However, previously existing IoT services have been usually developed based on vertical platforms, whose sharing and exchange of data is limited within each industry domain, for example, healthcare. Such problem is called 'data silo', and considered one of crucial issues to be solved for the success of establishing IoT ecosystems. Also, IoT services may need to dynamically organize their services according to the change of status of connected devices due to their mobility and dynamic network connectivity. We propose a way of dynamically composing IoT services under the concept of WoT (Web of Things) where heterogeneous devices across different industries are fully integrated into the Web. Our approach allows developers to create IoT services or mash them up in an efficient way using Web objects registered into multiple standardized horizontal IoT platforms where their resources are discoverable and accessible. A Web-based service composition tool is developed to evaluate the practical feasibility of our approach under real-world service development.

• Journal of Biomedical Engineering Research
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• v.28 no.6
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• pp.803-810
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• 2007

Although synthetic aperture focusing techniques can improve the spatial resolution of ultrasound imaging, they have not been employed in a commercial product because they require a real-time N-channel beamformer with a tremendously increased hardware complexity for simultaneous beamforming along M multiple lines. In this paper, a hardware-efficient beamformer architecture for synthetic aperture focusing is presented. In contrast to the straightforward design using NM delay calculators, the proposed method utilizes only M delay calculators by sharing the same values among the focusing delays which should be calculated at the same time between the N channels for all imaging points along the M scan lines. In general, synthetic aperture beamforming requires M 2-port memories. In the proposed beamformer, the input data for each channel is first upsampled with a 4-fold interpolator and each polyphase component of the interpolator output is stored into a 2-port memory separately, requiring 4M 2-port memories for each channel. By properly limiting the area formed with the synthetic aperture focusing, the input memory buffer can be implemented with only 4 2-port memories and one short multi-port memory.

• The KIPS Transactions:PartC
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• v.14C no.4
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• pp.341-348
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• 2007

Even though the secret information stored in home device in home network must be handled very safely and carefully, we have no measure for protecting the secret information without additional hardware support. Since already many home devices without consideration of the security have been used, the security protection method for those devices have to be required. In this paper, we suggest two schemes that protect the security information using networking function without additional hardware support, and those hybrid method to supplement the defects of each scheme. We also consider the our proposals in the aspects of security and cost.

• Journal of Power Electronics
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• v.18 no.2
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• pp.502-510
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• 2018

A circulating current is a major problem caused by directly connecting voltage-source inverters (VSIs) in parallel. This circulating current occurs as a zero-sequence current between the inverters by specific switch states. Several studies have presented alternatives using hardware and software methods. When coupled inductors (CIs) are employed for the high-frequency circulating current, a controller is required to prevent the low-frequency circulating current from saturating the CIs. In this study, the zero-sequence circulating current and its alternatives are investigated using hardware and mathematical description. A high-performance circulating current controller is proposed by applying a repetitive controller to the zero-sequence current control loop. The proposed controller can effectively minimize the low-frequency circulating current without any data sharing between the inverters in unfavorable conditions. It can also be applicable to the modular configuration of parallel three-phase VSIs. Experimental results verify the performance of the proposed controller.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.237-240
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• 2012

This paper describes an implementation of ARIA crypto algorithm which is a KS (Korea Standards) block cipher algorithm. The ARIA crypto-core supports three master key lengths of 128/192/256-bit specified in the standard and the four modes of operation including ECB, CBC, CTR and OFB. To reduce hardware complexity, a hardware sharing is employed, which shares round function in encryption/decryption module with key initialization module. The ARIA crypto-core is verified by FPGA implementation, the estimated throughput is about 1.07 Gbps at 167 MHz.