• Journal of KIISE:Computing Practices and Letters
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• v.8 no.6
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• pp.717-726
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• 2002

In this study, we analyze hardware implementation schemes of the ARS(Advanced Encryption Standard-128) algorithm that has recently been selected as the standard cypher algorithm by NIST(National Institute of Standards and Technology) . The implementation schemes include the basic architecture, loop unrolling, inner-round pipelining, outer-round pipelining and resource sharing of the S-box. We used MaxPlus2 9.64 for VHDL design and simulations and FLEX10KE-family FPGAs produced by Altera Corp. for implementations. According to the results, the four-stage inner-round pipelining scheme shows the best performance vs. cost ratio, whereas the loop unrolling scheme shows the worst.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.9 no.5
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• pp.1642-1661
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• 2015

Wireless mesh networks are a special type of broadcast networks which cover the qualifications of both ad-hoc as well as infrastructure mode networks. These networks offer connectivity to the last mile through hop to hop communication and by comparatively reducing the cost of infrastructure in terms of wire and hardware. Channel assignment has always been the focused area for such networks specifically when using non-overlapping channels and sharing radio frequency spectrum while using multiple radios. It has always been a challenge for mesh network on impartial utilization of the resources (channels), with the increase in users. The rational utilization of multiple channels and multiple radios, not only increases the overall throughput, capacity and scalability, but also creates significant complexities for channel assignment methods. For a better understanding of research challenges, this paper discusses heuristic methods, measurements and channel utilization applications and also examines various researches that yield to overcome this problem. Finally, we highlight prospective directions of research.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.4
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• pp.237-250
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• 2015

This paper describes a hardware-oriented algorithm and its conceptual implementation in a real-time speed limit traffic sign detection system on an automotive-oriented field-programmable gate array (FPGA). It solves the training and color dependence problems found in other research, which saw reduced recognition accuracy under unlearned conditions when color has changed. The algorithm is applicable to various platforms, such as color or grayscale cameras, high-resolution (4K) or low-resolution (VGA) cameras, and high-end or low-end FPGAs. It is also robust under various conditions, such as daytime, night time, and on rainy nights, and is adaptable to various countries' speed limit traffic sign systems. The speed limit traffic sign candidates on each grayscale video frame are detected through two simple computational stages using global luminosity and local pixel direction. Pipeline implementation using results-sharing on overlap, application of a RAM-based shift register, and optimization of scan window sizes results in a small but high-performance implementation. The proposed system matches the processing speed requirement for a 60 fps system. The speed limit traffic sign recognition system achieves better than 98% accuracy in detection and recognition, even under difficult conditions such as rainy nights, and is implementable on the low-end, low-cost Xilinx Zynq automotive Z7020 FPGA.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.11
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• pp.1713-1718
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• 2013

In this paper we implement collision avoidance using an artificial potential field and remote control of a mobile robot through ROS(Robot Operating System) among the robot's middleware. We also apply dynamic reconfigure to a node of collision avoidance. The main purposes of ROS are sharing and cooperation. In order to make to fit the purpose of ROS, the hardware that frequently is used in the robot such as LRF and joystick, were reused as node that provide in the ROS.

• Korea Information Processing Society Review
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• v.11 no.6
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• pp.56-75
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• 2004

In this article we address some system characteristics and challenging issues in developing Context-aware Middleware for Ubiquitous Computing. The functionalities of a Context-aware Middleware includes gathering context data from hardware/software sensors, reasoning and inferring high-level context data, and disseminating/delivering appropriate context data to interested applications/services. The Middleware should facilitate the query, aggregation, and discovery for the contexts, as well as facilities to specify their privacy policy. Following a formal context model using ontology would enable syntactic and semantic interoperability, and knowledge sharing between different domains. Moddleware should also provide different kinds of context classification mechanical as pluggable modules, including rules written in different types of logic (first order logic, description logic, temporal/spatial logic, fuzzy logic, etc.) as well as machine-learning mechanical (supervised and unsupervised classifiers). Different mechanisms have different power, expressiveness and decidability properties, and system developers can choose the appropriate mechanism that best meets the reasoning requirements of each context. And finally, to promote the context-trigger actions in application level, it is important to provide a uniform and platform-independent interface for applications to express their need for different context data without knowing how that data is acquired. The action could involve adapting to the new environment, notifying the user, communicating with another device to exchange information, or performing any other task.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.7
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• pp.1193-1203
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• 2016

This paper proposes a droop control scheme to compensate the unbalanced line-to-line voltage of unbalanced 3-phase load which is coupled with two inverter-based distributed generations through unequal impedance lines. Unbalanced line-to-line load voltages occur due to using single-phase loads, which brings about bad effects on the coupled inverters and the distributed generations. In order to compensate the unbalanced line-to-line voltages, a positive sequence voltage control was used for sharing the active and reactive power and a negative sequence control was used for reducing the negative sequence voltage. The feasibility of the proposed scheme was first verified by computer simulations, and then experiments with a hardware set-up built in the lab. The experimental results were compared with the simulation results to confirm the feasibility of the proposed scheme.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.5 no.1
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• pp.5-23
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• 2011

One inevitable problem in Ad Hoc networks is the limited battery capacity, which explains why portable devices might shut down suddenly when the power of hardware is depleted. Hence, how to decrease the power consumption is an important issue in ad hoc networks. With the development of wireless technology, mobile devices can transmit voices, surf the Internet, download entertaining stuffs, and even support some P2P applications, like sharing real-time streaming. In order to keep the quality stable, the transmission must be continuous and it is thus necessary to select some managers to coordinate all nodes in a P2P community. In addition to assigning jobs to the staffs (children) when needed, these managers (ancestors) are able to reappoint jobs in advance when employees retire. This paper proposed a mechanism called Cluster-based Power Management (CPM) to stabilize the transmissions and increase Time to Live (TTL) of mobile hosts. In our new proposed method, we establish the clusters according to every node's joining order and capability, and adjust their sleep time dynamically through three different mathematical models. Our simulation results reveal that this proposed scheme not only reduces the power consumption efficiently, but also increases the total TTLs evidently.

• KIPS Transactions on Computer and Communication Systems
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• v.3 no.12
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• pp.443-448
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• 2014

This paper is a study related to fault tolerant design based on PSTR using virtualization techniques. If the fault tolerant PSTR based on virtualization techniques is implemented the communication performance between primary and shadow will improves and monitoring function is easy to available about activities of primary and shadow. The legacy PSTR model is implemented in its hardware. The primary play a main role and shadow play a switched action when the errors occurrs in the primary. The switched action of shadow make it possible to restart the primary function newly. This paper implements fault tolerant primary-shadow model using virtualization techniques on the embedded environment.

• Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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• v.37 no.6
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• pp.445-452
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• 2019

In this study, parallel processing codes of k-means clustering algorithm were developed and implemented in a PC-cluster for unsupervised classification of large satellite images. We implemented intra-node code using multicores of CPU (Central Processing Unit) based on OpenMP (Open Multi-Processing), inter-nodes code using a PC-cluster based on message passing interface, and hybrid code using both. The PC-cluster consists of one master node and eight slave nodes, and each node is equipped with eight multicores. Two operating systems, Microsoft Windows and Canonical Ubuntu, were installed in the PC-cluster in turn and tested to compare parallel processing performance. Two multispectral satellite images were tested, which are a medium-capacity LANDSAT 8 OLI (Operational Land Imager) image and a high-capacity Sentinel 2A image. To evaluate the performance of parallel processing, speedup and efficiency were measured. Overall, the speedup was over N / 2 and the efficiency was over 0.5. From the comparison of the two operating systems, the Ubuntu system showed two to three times faster performance. To confirm that the results of the sequential and parallel processing coincide with the other, the center value of each band and the number of classified pixels were compared, and result images were examined by pixel to pixel comparison. It was found that care should be taken to avoid false sharing of OpenMP in intra-node implementation. To process large satellite images in a PC-cluster, code and hardware should be designed to reduce performance degradation caused by file I / O. Also, it was found that performance can differ depending on the operating system installed in a PC-cluster.

• The KIPS Transactions:PartA
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• v.16A no.2
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• pp.113-124
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• 2009

With increasing multicore system, much effort has been put on the performance improvement of its application. Because multicore system has multiple processing devices in one system, its processing power increases compared to the single core system. However in many cases the advantages of multicore can not be exploited fully because the existing software and hardware were designed to be suitable for single core. When the existing software runs on multicore, its performance improvement is limited by the bottleneck of sharing resources and the inefficient use of cache memory on multicore. Therefore, according as the number of core increases, it doesn't show performance improvement and shows performance drop in the worst case. In this paper we propose a method of performance improvement of multicore system by applying Flow-Level Parallelism to the existing TCP/IP network application and operating system. The proposed method sets up the execution environment so that each core unit operates independently as much as possible in network application, TCP/IP stack on operating system, device driver, and network interface. Moreover it distributes network traffics to each core unit through L2 switch. The proposed method allows to minimize the sharing of application data, data structure, socket, device driver, and network interface between each core. Also it allows to minimize the competition among cores to take resources and increase the hit ratio of cache. We implemented the proposed methods with 8 core system and performed experiment. Experimental results show that network access speed and bandwidth increase linearly according to the number of core.