• 한국통신학회논문지
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• 제11권4호
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• pp.251-258
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• 1986

TV와 같은 영상신호에는 중복도가 많이 존재하며, 이를 줄이기 위한 여러가지 방법들이 연구되고 있다. 본 논문에서는 Hadamard 변환을 이용하여 computer simulation과 실험 모델을 제작하여 데이터 압축에 관해 연구하였다. Hadamard matrix는 +1과 -1로 구성되며, row vector들은 서로 orthogonal하고 변환된 signal을 계산하기 위해서는 가산과 감산만이 필요하기 때문에 가산뿐 아니라 승산이 필요한 Fourier transform등 다른 orthogonal transform 에 비해 hardware구성이 용이하다. 링컨데이타 (64$ imes$64)를 8차와 16차 Hadamard 변환으로 simulation하였고, 8차를 hardware로 구성하였으며 이 경우 이론과 실험을 통해 연구한 결과 좋은 화질을 얻기 위해서는 2.0bits/sample가 필요했다.

• 한국항행학회논문지
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• 제14권1호
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• pp.87-92
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• 2010

항공 임베디드 시스템은 고신뢰성 설계가 매우 중요하다. 본 논문에서는 고신뢰성 항공 임베디드 시스템 연구를 위하여 Triple Modular Redundancy(TMR) 구조의 하드웨어를 설계하였다. TMR 구조의 하드웨어가 단일 프로세서 구조의 하드웨어보다 얼마나 신뢰성이 향상 되었는지를 연구하기 위하여, ARM 프로세서와 TMR ARM 프로세서의 축소된 형태의 시뮬레이션 모델을 개발하였고 각각의 신뢰성을 평가하는 연구를 수행하였다. 신뢰성 평가는 RTL을 이용한 시뮬레이션 기반 오류 주입 시뮬레이션 기법을 이용하였다. 주입된 오류별로 타겟 시스템의 상태변화를 분석하여, 오류 복구비율을 계산하였다. 실험결과 TMR ARM의 오류복구 능력은 ARM에 비해 최대 10배 이상 향상되었으며, 특히 permanent fault에서 더 강인함을 확인 하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(1)
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• pp.267-270
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• 2000

In this paper, we consider the simple redundant structures with the function of hardware based active/standby control. The system includes two switch modules. The switch module is connected to a data bus, but only the active switch module has control of the data bus. The standby unit takes over the function of the active unit when the active unit failure or mode command are asserted. And this paper illustrate the high-speed router system and the overall redundant system architecture. The proposed redundant architecture for 80G Router system is verified and implemented with experiment.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(I)
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• pp.213-215
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• 1987

As a means of improving the reliability of the analog type controller for the thermal power plant, an efficient method is proposed, which is to place the hardware redundancy, i.e. a back-up controller with fault detecting capability. FTCS is implemented by using multi-processors and it is experimentally verified that the back-up controller takes over the role of the original controller, controlling the faulty loop.

• International Journal of Fuzzy Logic and Intelligent Systems
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• 제4권1호
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• pp.34-39
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• 2004

Huffman coding which has been used in many data compression algorithms is a popular data compression technique used to reduce statistical redundancy of a signal. It has been proposed that the Huffman algorithm can decode efficiently using characteristics of the Huffman tables and patterns of the Huffman codeword. We propose a new Huffman decoding algorithm which used a multi way tree search and present an efficient hardware implementation method. This algorithm has a small logic area and memory space and is optimized for high speed decoding. The proposed Huffman decoding algorithm can be applied for many multimedia systems such as MPEG audio decoder.

• 한국철도학회논문집
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• 제9권6호
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• pp.725-731
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• 2006

Hot Standby sparing system detecting faults by using software, and being tolerant any faults by using Hardware Redundancy is difficult to perform quantitative reliability prediction and to detect real time faults. Therefore, this paper designs Hot Standby sparing system using hardware basis self checking logic in order to overcome this problem. It also performs failure mode analysis of Hot Standby sparing system with designed self checking logic by using FMEA (Failure Mode Effect Analysis), and identifies reliability assessment of the controller designed by quantifying the numbers of failure development by using FTA (Fault Tree Analysis)

• Journal of Power Electronics
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• 제16권2호
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• pp.522-531
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• 2016

This paper proposes a new NLC (Nearest Level Control) scheme for MMCs (Modular Multilevel Converters), which offers voltage ripple reductions in the DC capacitor of the SM (Sub-Module), the output voltage harmonics, and the switching losses. The feasibility of the proposed NLC was verified through computer simulations. Based on these simulation results, a hardware prototype of a 10kVA, DC-1000V MMC was manufactured in the lab. Experiments were conducted to verify the feasibility of the proposed NLC in an actual hardware environment. The experimental results were consistent with the results obtained from the computer simulations.

• 한국산업정보학회:학술대회논문집
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• 한국산업정보학회 1997년도 추계학술대회 발표논문집:21세기를 향한 정보통신 기술의 전망
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• pp.417-433
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• 1997

A real-time operating system has focused primary on techniques to minimize processing time, with a secondary emphasis on system reliability issues. Conversely, fault-tolerant system has concentrated on using recourse and information redundancy to maximize the availability and reliability of the system, with a lesser emphasis on performance. We have developed a fault-tolerant and real-time operations system which support a powerful concurrent runtime environment under the above requirements. In this paper, we present an overview of real-time systems, design and implementation of a duplex architecture using advanced concepts and technologies such as fast " fault detection", "fault isolation" and "fault recovery" Because the duplex architecture has two dentical hardware elements and has several recovery steps and hierarchy to facilitate a fast recovery which must be proceeded by a prompt fault detection and isolation. Thus it makes possible to minimize the overhead of the systems including hardware and software and guarantee the service continuity of he systems.

• 한국컴퓨터정보학회논문지
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• 제20권10호
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• pp.1-5
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• 2015

Based on the dual hardware and software with distributed recovery blocks, the centralized type fault tolerant store management system(SMS) was proposed. As a result of trade off study related to mutiplex hardware system design, dual single board computer(SBC) was adapted. To verify redundancy function of the proposed structure, the prototype SMS and weapon simulator were used. The proposed SMS operated normally without being affected by a primary SBC failure. The switching time from primary SBC to shadow SBC was within 200 ms. The reliability of the proposed SMS was predicted and compared with the non fault tolerant SMS, thereby it was proved that the proposed SMS has a higher reliability than the non fault tolerant system within effective range.

• Journal of Multimedia Information System
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• 제5권4호
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• pp.273-276
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• 2018

In video compression standards, the entropy coding is essential to the high performance compression because redundancy of data symbols is removed. Binary arithmetic coding is one of high performance entropy coding methods. However, the dependency between consecutive binary symbols prevents improving the throughput. For the throughput enhancement, a new probability model is proposed for encoding multi-symbols at one time. In the proposed method, multi-symbol encoder is implemented with only adders and shifters, and the multiplication table for interval subdivision of binary arithmetic coding is removed. Compared to the compression ratio of CABAC of H.264/AVC, the performance degradation on average is only 1.4% which is negligible.