• Journal of the Korean Society for Library and Information Science
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• v.49 no.2
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• pp.255-274
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• 2015

This study aims to define the user experience and to evaluate the usability toward electronic publication for education and research. As research methods, After total 20 people of 10 undergraduate students and 10 graduate students were randomly selected as the subjects, the research was conducted by using the in-depth interview and the e-book reader experimental method. As the results of analysis about subjective preferences in case of using academic resources, The subject relevance and understandability were responded as most important factors for selecting academic resources. And the most frequent purposes for using academic resources were to perform an assignment and to write an article. As the results of analysis about the user experience for using the print media and electronic media, the user experience of the print media is more positive than the electronic media and especially these results were caused by academic situation. Many subjects responded that the electronic media is more inconvenient in case of using academic resources. As a result of the e-book reader usability test, the hardware test score (3.47) is higher than the software test score (3.31).

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.48 no.8
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• pp.42-50
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• 2011

Recently, research activities on the future internet are being actively performed in foreign and domestic. In domestic, ETRI and 4 universities are focused on implementation of a testbed for research on the future internet named as 'FiRST(Future Internet Research for Sustainable Testbed)'. In the 'FiRST' project, 4 universities are performing a project in collaboration named as 'FiRST@PC' project that is for an implementation of the testbed using the programmable platform-based openflow switches. Currently, the research on the virtualization of the testbed is being performed that has a purpose for supporting an isolated network to individual researcher. In this paper, we implemented a traffic scheduler for providing QoS by using the programmable platform that performs a hardware-based packet processing and we are implemented a testbed using that traffic scheduler. We perform a performance evaluation of the traffic scheduler on the testbed. As a result, we show that the hardware-based NetFPGA scheduler can provide reliable and stable QoS to virtualized networks of the Future Internet Testbed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.4
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• pp.795-803
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• 2017

This paper describes a dual-standard cryptographic processor that efficiently integrates two block ciphers ARIA and AES into a unified hardware. The ARIA-AES crypto-processor was designed to support 128-b and 256-b key sizes, as well as four modes of operation including ECB, CBC, OFB, and CTR. Based on the common characteristics of ARIA and AES algorithms, our design was optimized by sharing hardware resources in substitution layer and in diffusion layer. It has on-the-fly key scheduler to process consecutive blocks of plaintext/ciphertext without reloading key. The ARIA-AES crypto-processor that was implemented with a $0.18{\mu}m$ CMOS cell library occupies 54,658 gate equivalents (GEs), and it can operate up to 95 MHz clock frequency. The estimated throughputs at 80 MHz clock frequency are 787 Mbps, 602 Mbps for ARIA with key size of 128-b, 256-b, respectively. In AES mode, it has throughputs of 930 Mbps, 682 Mbps for key size of 128-b, 256-b, respectively. The dual-standard crypto-processor was verified by FPGA implementation using Virtex5 device.

• Journal of the Institute of Convergence Signal Processing
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• v.15 no.2
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• pp.70-75
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• 2014

Recently, the demand for high-integrated, low-powered, and high-powered SoC design has been increasing due to the multi-functionality and the miniaturization of digital devices and the high capacity of service informations. With the rapid evolution of the system, the required hardware performances have become diversified, the FPGA system has been increasingly adopted for the rapid verification, and SoC system using the FPGA and the ARM core for control has been growingly chosen. While the AXI bus is used in these kinds of systems in various ways, it is traditionally designed with AXI slave structure. In slave structure, there are problems with the CPU resources because CPU is continually involved in the data transfer and can't be used in other jobs, and with the decreased transmission efficiency because the time not used of AXI bus beomes longer. In this paper, an efficient AXI master interface is proposed to solve this problem. The simulation results show that the proposed system achieves reductions in the consumption clock by an average of 51.99% and in the slice by 31% and that the maximum operating frequency is increased to 107.84MHz by about 140%.

• KIPS Transactions on Computer and Communication Systems
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• v.6 no.5
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• pp.219-230
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• 2017

General-Purpose Graphics Processing Units (GPGPUs) build massively parallel architecture and apply multithreading technology to explore parallelism. By using programming models like CUDA, and OpenCL, GPGPUs are becoming the best in exploiting plentiful thread-level parallelism caused by parallel applications. Unfortunately, modern GPGPU cannot efficiently utilize its available hardware resources for numerous general-purpose applications. One of the primary reasons is the inefficiency of existing warp/thread block schedulers in hiding long latency instructions, resulting in lost opportunity to improve the performance. This paper studies the effects of hardware thread scheduling policy on GPGPU performance. We propose a novel warp scheduling policy that can alleviate the drawbacks of the traditional round-robin policy. The proposed warp scheduler first classifies the warps of a thread block into two groups, warps with long latency and warps with short latency and then schedules the warps with long latency before the warps with short latency. Furthermore, to support the proposed warp scheduler, we also propose a supplemental technique that can dynamically reduce the number of streaming multiprocessors to which will be assigned thread blocks when encountering a high contention degree at the memory and interconnection network. Based on our experiments on a 15-streaming multiprocessor GPGPU platform, the proposed warp scheduling policy provides an average IPC improvement of 7.5% over the baseline round-robin warp scheduling policy. This paper also shows that the GPGPU performance can be improved by approximately 8.9% on average when the two proposed techniques are combined.

• Journal of the Korean association of regional geographers
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• v.22 no.3
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• pp.499-514
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• 2016

Social enterprise is defined as a sort of companies that pursue both publicity and profitability. It is usual that their business activities and viability are dependent upon localized resources in terms of a labor market, raw material procurement and sales market. Also, the characteristics and viability of social enterprises based on local resources within the framework of social economy policy. The social economic policy in Korea is generally treated as means of local developments. This paper aims to examine the localness and socio-economic foundation of social enterprises which are located in the west of Gyeongnam province in Korea and to provide policy recommendations for promoting local resource-based social enterprises. The selection of the case study firms was chosen by considering various factors such as the viability of the firm, location of a company and the types of organization. The research result shows that most of local social enterprises had a viability and profitability to effectively utilize local resources. But it is claimed that the government policy for promoting local social enterprises reveals some limitations to promoting effectively local social enterprises. First, it is necessary to limit the qualification of applying to the government support program. Second, financial support should be changed from hardware-centered programs to software-centered programs such as training and education for human resource development and the business consulting. Finally, it is necessary for the government policy to focus on follow-up programs for firms which are no more capable of receiving the government financial support. For these firms, the government policy needs to focus on facilitating activities of cooperation between local universities and local social enterprise.

• 한국지구물리탐사학회:학술대회논문집
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• 2004.08a
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• pp.49-69
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• 2004

One of the important roles of geophysical exploration in archeological survey may be to provide the subsurface information for effective and systematic excavations of historical remains. Ground Penetrating Radar (GPA) can give us images of shallow subsurface structure with high resolution and is regarded as a useful and important technology in archeological exploration. Since the buried cultural relics are the three-dimensional (3-D) objects in nature, the 3-D or areal survey is more desirable in archeological exploration. 3-D GPR survey based on the very dense data in principle, however, might need much higher cost and longer time of exploration than the other geophysical methods, thus it could have not been applied to the wide area exploration as one of routine procedures. Therefore, it is important to develop an effective way of 3-D GPR survey. In this study, we applied 3-D GPR method to investigate the possible historical remains of Baekje Kingdom at Gatap-Ri, Buyeo city, prior to the excavation. The principal purpose of the investigation was to provide the subsurface images of high resolution for the excavation of the surveyed area. Besides this, another purpose was to investigate the applicability and effectiveness of the continuous data acquisition system which was newly devised for the archeological investigation. The system consists of two sets of GPR antennas and the precise measurement device tracking the path of GPR antenna movement automatically and continuously Besides this hardware system, we adopted a concept of data acquisition that the data were acquired arbitrary not along the pre-established profile lines, because establishing the many profile lines itself would make the field work much longer, which results in the higher cost of field work. Owing to the newly devised system, we could acquire 3-D GPR data of an wide area over about $17,000 m^2$ as a result of the just two-days field work. Although the 3-D GPR data were gathered randomly not along the pre-established profile lines, we could have the 3-D images with high resolution showing many distinctive anomalies which could be interpreted as old agricultural lands, waterways, and artificial structures or remains. This case history led us to the conclusion that 3-D GPR method can be used easily not only to examine a small anomalous area but also to investigate the wider region of archeological interests. We expect that the 3-D GPR method will be applied as a one of standard exploration procedures to the exploration of historical remains in Korea in the near future.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.9
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• pp.512-522
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• 2003

For a time-multiplexed FPGA, a circuit is partitioned into several subcircuits, so that they temporally share the same physical FPGA device by hardware reconfiguration. In these architectures, all the hardware reconfiguration information called contexts are generated and downloaded into the chip, and then the pre-scheduled context switches occur properly and timely. Typically, the size of the chip required to implement the circuit depends on both the maximum number of the LUT blocks required to implement the function of each subcircuit and the maximum number of micro-registers to store results over context switches in the same time. Therefore, many partitioning or synthesis methods try to minimize these two factors. In this paper, we present a new estimation technique to find the lower bound on the number of micro-registers which can be obtained by any synthesis methods, respectively, without performing any actual synthesis and/or design space exploration. The lower bound estimation is very important in sense that it greatly helps to evaluate the results of the previous work and even the future work. If the estimated lower bound exactly matches the actual number in the actual design result, we can say that the result is guaranteed to be optimal. In contrast, if they do not match, the following two cases are expected: we might estimate a better (more exact) lower bound or we find a new synthesis result better than those of the previous work. Our experimental results show that there are some differences between the numbers of micro-registers and our estimated lower bounds. One reason for these differences seems that our estimation tries to estimate the result with the minimum micro-registers among all the possible candidates, regardless of usage of other resources such as LUTs, while the previous work takes into account both LUTs and micro-registers. In addition, it implies that our method may have some limitation on exact estimation due to the complexity of the problem itself in sense that it is much more complicated than LUT estimation and thus needs more improvement, and/or there may exist some other synthesis results better than those of the previous work.

• Asia-Pacific Journal of Business Venturing and Entrepreneurship
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• v.18 no.5
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• pp.91-107
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• 2023

Lean startup is a concept that combines the words "lean," meaning an efficient way of running a business, and "startup," meaning a new business. It is often cited as a strategy for minimizing failure in early-stage businesses, especially in software-based startups. By scrutinizing the case of a startup L, this study suggests that lean startup methodology(LSM) can be useful for hardware and manufacturing companies and identifies ways for early startups to successfully implement LSM. To this end, the study explained the core of LSM including the concepts of hypothesis-driven approach, BML feedback loop, minimum viable product(MVP), and pivot. Five criteria to evaluate the successful implementation of LSM were derived from the core concepts and applied to evaluate the case of startup L . The early startup L pivoted its main business model from defecation alert system for patients with limited mobility to one for infants or toddlers, and finally to a smart bottle for infants. In developing the former two products, analyzed from LSM's perspective, company L neither established a specific customer value proposition for its startup idea and nor verified it through MVP experiment, thus failed to create a BML feedback loop. However, through two rounds of pivots, startup L discovered new target customers and customer needs, and was able to establish a successful business model by repeatedly experimenting with MVPs with minimal effort and time. In other words, Company L's case shows that it is essential to go through the customer-market validation stage at the beginning of the business, and that it should be done through an MVP method that does not waste the startup's time and resources. It also shows that it is necessary to abandon and pivot a product or service that customers do not want, even if it is technically superior and functionally complete. Lastly, the study proves that the lean startup methodology is not limited to the software industry, but can also be applied to technology-based hardware industry. The findings of this study can be used as guidelines and methodologies for early-stage companies to minimize failures and to accelerate the process of establishing a business model, scaling up, and going global.

• Aerospace Engineering and Technology
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• v.4 no.2
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• pp.21-26
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• 2005

In airframe structural tests, a control system which has many control channels and a data acquisition system which has many data acquisition channels are used. The more it is used many channels in airframe structural test, the more hardware resources are added in test system. Before test load is applied in test article, test engineer must check test system and components. Therefore, many problems which be likely to happen to system can be minimized. The checking method of test system and components is calibration verification. In this paper, it is described that calibration verification concept and method in relation to airframe structural test controller components.(MTS Aero90 Multifunction Input Output Processor and 497.22 Dual DC Conditioner)