• Electronics and Telecommunications Trends
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• v.32 no.6
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• pp.83-95
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• 2017

The trend of manycore hardware has recently evolved more quickly than expected. However, an operating system, which is software used for managing computer resources, is still optimized for a multicore system. To handle this issue, we started a research project called 'Research on High Performance and Scalable Manycore Operating Systems' in 2014. This article briefly examines the technology trends of manycore hardware and operating systems, and introduces the research areas and outcomes during the first stage of the project(2014-2017). The core technologies improving the performance scalability of manycore systems are publicly available, and anyone can use the source code or apply the ideas of the core technique to other research activities. In addition, the research plans of the second stage of the project(2018-2021) are also included.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.62 no.3
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• pp.322-331
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• 2013

This paper describes the development of the pilot plant of distributed intelligent management system for a microgrid. For optimal control and management of microgrids, intelligent agents area applied to the microgrid management system. Each agent includes intelligent algorithms to make decisions on behalf of the corresponding microgrid entity such as distributed generators, local loads, and so on. To this end, each agent has its own resources to evaluate the system conditions by collecting local information and also communicating with other agents. This paper presents key features of the data communication and management of the developed pilot plant such as the construction of mesh network using local wireless communication techniques, the autonomous agent coordination schemes using plug-and-play functions of agents and contract net protocol (CNP) for decision-making. The performance of the pilot plant and developed algorithms are verified via real-time microgrid test bench based on hardware-in-the-loop simulation systems.

• ETRI Journal
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• v.28 no.3
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• pp.320-328
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• 2006

Using biometrics to verify a person's identity has several advantages over the present practice of personal identification numbers (PINs) and passwords. To gain maximum security in a verification system using biometrics, the computation of the verification as well as the storing of the biometric pattern has to take place in a smart card. However, there is an open issue of integrating biometrics into a smart card because of its limited resources (processing power and memory space). In this paper, we propose a speaker verification algorithm using a support vector machine (SVM) with a very few features, and implemented it on a 32-bit smart card. The proposed algorithm can reduce the required memory space by a factor of more than 100 and can be executed in real-time. Also, we propose a hardware design for the algorithm on a field-programmable gate array (FPGA)-based platform. Based on the experimental results, our SVM solution can provide superior performance over typical speaker verification solutions. Furthermore, our FPGA-based solution can achieve a speed-up of 50 times over a software-based solution.

• Journal of IKEEE
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• v.17 no.1
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• pp.36-43
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• 2013

This paper proposes a motion estimation algorithm with run-time adaptive workload control. It has optimized performance within limited hardware resources while guaranteeing hard realtime operation. It performs maximum searches within hard realtime constraints, since it determines search steps and workload adaptively. It reduces the hardware size to 1/4~1/400 of conventional algorithms, while its PSNR degradation is only 0.02~0.44 dB. It can be easily applied to most conventional fast algorithms, so it is useful to design realtime encoder chips.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.13 no.2
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• pp.668-685
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• 2019

Provision of higher throughput without sacrificing consistency guarantees in replication systems is a critical problem. In this paper, we propose a novel approach called Bidirectional Chain Replication (BCR) to improve throughput in traditional Chain Replication (CR) through better utilization of computing and communication resources of the chain. Unlike CR where the whole replicated data store is treated as a single unit, in BCR the replicated shared data at each server in the chain is split into two disjoint Logical Partitions ($LP_1$, $LP_2$). This forms two chains running concurrently on the same hardware in two opposite directions; the first chain ($CR_1$) exclusively manipulates data objects in $LP_1$, while the second chain ($CR_2$) exclusively manipulates data objects in $LP_2$, therefore, conflict is avoided and concurrency is guaranteed. The simultaneous employment of these two chains results in better utilization of hardware in the sense that the two chains can evenly share the workload, hence, throughput can be improved without sacrificing consistency. Experimental results showed an improvement of approximately 85% in throughput of BCR over CR.

• Journal of Sensor Science and Technology
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• v.32 no.4
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• pp.246-251
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• 2023

Internet of Things (IoT) systems process signals from various sensors using signal processing algorithms suitable for the signal characteristics. To analyze complex signals, these systems usually use signal processing algorithms in the frequency domain, such as fast Fourier transform (FFT), filtering, and short-time Fourier transform (STFT). In this study, we propose a multi-mode sensor signal processor (SSP) accelerator with an FFT-based hardware design. The FFT processor in the proposed SSP is designed with a radix-2 single-path delay feedback (R2SDF) pipeline architecture for high-speed operation. Moreover, based on this FFT processor, the proposed SSP can perform filtering and STFT operation. The proposed SSP is implemented on a field-programmable gate array (FPGA). By sharing the FFT processor for each algorithm, the required hardware resources are significantly reduced. The proposed SSP is implemented and verified on Xilinxh's Zynq Ultrascale+ MPSoC ZCU104 with 53,591 look-up tables (LUTs), 71,451 flip-flops (FFs), and 44 digital signal processors (DSPs). The FFT, filtering, and STFT algorithm implementations on the proposed SSP achieve 185x average acceleration.

• Tunnel and Underground Space
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• v.28 no.6
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• pp.547-554
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• 2018

Using crowdsourced sensor data collection technique, it is possible to collect high-density ground vibration data which is difficult to obtain by conventional methods. In this study, we have developed a crowdsourced ground vibration data collection system using MEMS sensors mounted on small electronic devices including smartphones, and implemented client and server based on the proposed infrastructure system design. The system is designed to gather vibration data quickly through Android-based smartphones or fixed devices based on Android Things, minimizing the usage of resource like power usage and data transmission traffic of the hardware.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.29 no.5
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• pp.961-971
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• 2019

Isolation between virtual machines in a cloud computing environment is an important security factor. The violation of isolation between virtual machines leads to interferences of shared resources and the implementation of covert channels. In this paper, the structure of Hyper-V hypervisor is analyzed to implement covert channels between virtual machines. Hyper-V uses a mutex technique for mutual exclusion between virtual machines. It indicates that isolation of virtual machines is violated and covert channels can be implemented due to mutex. We implemented several covert channels by designing a method for searching mutex resources applicable to Hyper-V with complex architectures. The mutex-based covert channel is not hardware dependent. If the covert channel is detected or defended, the defensive technique can be avoided by using the other covert channel among several covert channels.

• Journal of IKEEE
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• v.25 no.1
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• pp.229-233
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• 2021

NPU in an embedded environment performs deep learning algorithms with few hardware resources. By using a technique that reuses data, deep learning algorithms can be efficiently computed with fewer resources. In previous studies, data is reused using a shifter in ScratchPad for data reuse. However, as the ScratchPad's bandwidth increases, the shifter also consumes a lot of resources. Therefore, we present a data reuse technique using the Buffer Round Robin method. By using the Buffer Round Robin method presented in this paper, the chip area could be reduced by about 4.7% compared to the conventional method.

• Journal of Sensor Science and Technology
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• v.30 no.1
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• pp.20-24
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• 2021

The electrocardiogram (ECG) is one of the most extensively employed signals used to diagnose and predict cardiovascular diseases (CVDs). In recent years, several deep learning (DL) models have been proposed to improve detection accuracy. Among these, deep neural networks (DNNs) are the most popular, wherein the features are extracted automatically. Despite the increment in classification accuracy, DL models require exorbitant computational resources and power. This causes the mapping of DNNs to be slow; in addition, the mapping is challenging for a wearable device. Embedded systems have constrained power and memory resources. Therefore full-precision DNNs are not easily deployable on devices. To make the neural network faster and more power-efficient, spiking neural networks (SNNs) have been introduced for fewer operations and less complex hardware resources. However, the conventional SNN has low accuracy and high computational cost. Therefore, this paper proposes a new binarized SNN which modifies the synaptic weights of SNN constraining it to be binary (+1 and -1). In the simulation results, this paper compares the DL models and SNNs and evaluates which model is optimal for ECG classification. Although there is a slight compromise in accuracy, the latter proves to be energy-efficient.