• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.1041-1043
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• 1993

Fuzzy logic based Control Theory has gained much interest in the industrial world, thanks to its ability to formalize and solve in a very natural way many problems that are very difficult to quantify at an analytical level. This paper shows a solution for treating membership function inside hardware circuits. The proposed hardware structure optimizes the memoried size by using particular form of the vectorial representation. The process of memorizing fuzzy sets, i.e. their membership function, has always been one of the more problematic issues for the hardware implementation, due to the quite large memory space that is needed. To simplify such an implementation, it is commonly [1,2,8,9,10,11] used to limit the membership functions either to those having triangular or trapezoidal shape, or pre-definite shape. These kinds of functions are able to cover a large spectrum of applications with a limited usage of memory, since they can be memorized by specifying very few parameters ( ight, base, critical points, etc.). This however results in a loss of computational power due to computation on the medium points. A solution to this problem is obtained by discretizing the universe of discourse U, i.e. by fixing a finite number of points and memorizing the value of the membership functions on such points [3,10,14,15]. Such a solution provides a satisfying computational speed, a very high precision of definitions and gives the users the opportunity to choose membership functions of any shape. However, a significant memory waste can as well be registered. It is indeed possible that for each of the given fuzzy sets many elements of the universe of discourse have a membership value equal to zero. It has also been noticed that almost in all cases common points among fuzzy sets, i.e. points with non null membership values are very few. More specifically, in many applications, for each element u of U, there exists at most three fuzzy sets for which the membership value is ot null [3,5,6,7,12,13]. Our proposal is based on such hypotheses. Moreover, we use a technique that even though it does not restrict the shapes of membership functions, it reduces strongly the computational time for the membership values and optimizes the function memorization. In figure 1 it is represented a term set whose characteristics are common for fuzzy controllers and to which we will refer in the following. The above term set has a universe of discourse with 128 elements (so to have a good resolution), 8 fuzzy sets that describe the term set, 32 levels of discretization for the membership values. Clearly, the number of bits necessary for the given specifications are 5 for 32 truth levels, 3 for 8 membership functions and 7 for 128 levels of resolution. The memory depth is given by the dimension of the universe of the discourse (128 in our case) and it will be represented by the memory rows. The length of a world of memory is defined by: Length = nem (dm(m)＋dm(fm) Where: fm is the maximum number of non null values in every element of the universe of the discourse, dm(m) is the dimension of the values of the membership function m, dm(fm) is the dimension of the word to represent the index of the highest membership function. In our case then Length=24. The memory dimension is therefore 128*24 bits. If we had chosen to memorize all values of the membership functions we would have needed to memorize on each memory row the membership value of each element. Fuzzy sets word dimension is 8*5 bits. Therefore, the dimension of the memory would have been 128*40 bits. Coherently with our hypothesis, in fig. 1 each element of universe of the discourse has a non null membership value on at most three fuzzy sets. Focusing on the elements 32,64,96 of the universe of discourse, they will be memorized as follows: The computation of the rule weights is done by comparing those bits that represent the index of the membership function, with the word of the program memor . The output bus of the Program Memory (μCOD), is given as input a comparator (Combinatory Net). If the index is equal to the bus value then one of the non null weight derives from the rule and it is produced as output, otherwise the output is zero (fig. 2). It is clear, that the memory dimension of the antecedent is in this way reduced since only non null values are memorized. Moreover, the time performance of the system is equivalent to the performance of a system using vectorial memorization of all weights. The dimensioning of the word is influenced by some parameters of the input variable. The most important parameter is the maximum number membership functions (nfm) having a non null value in each element of the universe of discourse. From our study in the field of fuzzy system, we see that typically nfm 3 and there are at most 16 membership function. At any rate, such a value can be increased up to the physical dimensional limit of the antecedent memory. A less important role n the optimization process of the word dimension is played by the number of membership functions defined for each linguistic term. The table below shows the request word dimension as a function of such parameters and compares our proposed method with the method of vectorial memorization[10]. Summing up, the characteristics of our method are: Users are not restricted to membership functions with specific shapes. The number of the fuzzy sets and the resolution of the vertical axis have a very small influence in increasing memory space. Weight computations are done by combinatorial network and therefore the time performance of the system is equivalent to the one of the vectorial method. The number of non null membership values on any element of the universe of discourse is limited. Such a constraint is usually non very restrictive since many controllers obtain a good precision with only three non null weights. The method here briefly described has been adopted by our group in the design of an optimized version of the coprocessor described in [10].

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.10
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• pp.4717-4737
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• 2017

Today, smart grids, smart homes, smart water networks, and intelligent transportation, are infrastructure systems that connect our world more than we ever thought possible and are associated with a single concept, the Internet of Things (IoT). The number of devices connected to the IoT and hence the number of traffic flow increases continuously, as well as the emergence of new applications. Although cutting-edge hardware technology can be employed to achieve a fast implementation to handle this huge data streams, there will always be a limit on size of traffic supported by a given architecture. However, recent cloud-based big data technologies fortunately offer an ideal environment to handle this issue. Moreover, the ever-increasing high volume of traffic created on demand presents great challenges for flow management. As a solution, flow aggregation decreases the number of flows needed to be processed by the network. The previous works in the literature prove that most of aggregation strategies designed for smart grids aim at optimizing system operation performance. They consider a common identifier to aggregate traffic on each device, having its independent static aggregation policy. In this paper, we propose a dynamic approach to aggregate flows based on traffic characteristics and device preferences. Our algorithm runs on a big data platform to provide an end-to-end network visibility of flows, which performs high-speed and high-volume computations to identify the clusters of similar flows and aggregate massive number of mice flows into a few meta-flows. Compared with existing solutions, our approach dynamically aggregates large number of such small flows into fewer flows, based on traffic characteristics and access node preferences. Using this approach, we alleviate the problem of processing a large amount of micro flows, and also significantly improve the accuracy of meeting the access node QoS demands. We conducted experiments, using a dataset of up to 100,000 flows, and studied the performance of our algorithm analytically. The experimental results are presented to show the promising effectiveness and scalability of our proposed approach.

• Journal of the Korean association of regional geographers
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• v.22 no.3
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• pp.499-514
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• 2016

Social enterprise is defined as a sort of companies that pursue both publicity and profitability. It is usual that their business activities and viability are dependent upon localized resources in terms of a labor market, raw material procurement and sales market. Also, the characteristics and viability of social enterprises based on local resources within the framework of social economy policy. The social economic policy in Korea is generally treated as means of local developments. This paper aims to examine the localness and socio-economic foundation of social enterprises which are located in the west of Gyeongnam province in Korea and to provide policy recommendations for promoting local resource-based social enterprises. The selection of the case study firms was chosen by considering various factors such as the viability of the firm, location of a company and the types of organization. The research result shows that most of local social enterprises had a viability and profitability to effectively utilize local resources. But it is claimed that the government policy for promoting local social enterprises reveals some limitations to promoting effectively local social enterprises. First, it is necessary to limit the qualification of applying to the government support program. Second, financial support should be changed from hardware-centered programs to software-centered programs such as training and education for human resource development and the business consulting. Finally, it is necessary for the government policy to focus on follow-up programs for firms which are no more capable of receiving the government financial support. For these firms, the government policy needs to focus on facilitating activities of cooperation between local universities and local social enterprise.

• Korean Security Journal
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• no.50
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• pp.241-261
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• 2017

Despite the trend and severity of industrial technology outflow crime, little research has been conducted about the effect of police force on that kind of crime in Korea. Consequently, this research preliminarily empirically examined relationship between foreign affairs police forces such as policemen, budget, establishing special investigation unit and the arrest of industrial technology outflow crime due to the limit of related data. Research findings can be summarized as follows. A statistically significant positive relationship was found between foreign police budget and the arrest of crime in the country. On the contrary, foreign police force is not significantly associated with the arrest and occurrence of crime overseas. Based on the result, the effect of the police force such as hardware factors including policemen, budget on the industrial technology outflow crime seemed to be weak. Consequently, considering police alternatives from previous researches, several implications such as reinforcement of foreign police force by increasing personnel and organizational innovation, enriching training program, strengthening the domestic and foreign cooperative network between police and related bodies can be suggested. Also, the improvement of the formal statistics on the industrial technology outflow crime and strenthening public relations can be recommended.

• The Transactions of the Korean Institute of Power Electronics
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• v.12 no.6
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• pp.456-464
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• 2007

This paper proposes a novel three-phase current-fed active clamp DC-DC converter for fuel cells. A single common active clamp branch is used to limit transient voltage across the three-phase full bridge and to realize zero-voltage switching(ZVS) in all switches. To apply for the power generation system current-fed type has been combined with the three-phase power conversion system. The proposed approach has the following advantages: an increase (by a factor of three) of input current and output voltage chopping frequencies; lower RMS current through the inverter switches with higher power transfer capability; reduction in size of reactive later components and the power conditioning system; better transformer utilization; increase of the system reliability. Therefore, the proposed three-phase current-fed active clamp DC-DC converter is appropriate for the boost type DC-DC converter for fuel cells and also applicable for the photovoltaic and battery charge system. The paper details the analysis, simulation and hardware implementation of the proposed system. Finally, experimental results with the proposed PWM strategy demonstrate the feasibility of the proposed scheme on a 500W prototype converter.

• The Journal of the Korea Contents Association
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• v.12 no.5
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• pp.10-21
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• 2012

The role of GPU has evolved from graphics-specific processing to general-purpose processing with the development of unified shader core architecture. Especially, execution methods for general-purpose parallel applications using GPU have been researched intensively, since the parallel hardware architecture can be utilized efficiently when the parallel applications are executed. However, current GPU architecture has limitations in executing general-purpose parallel applications, since the GPU is not specialized for general-purpose computing yet. To improve the GPU performance when general-purpose parallel applications are executed, the GPU architecture should be evolved. In this work, we analyze the GPU performance according to the architecture varying the number of cores and clock frequency. Our simulation results show that the GPU performance improves by up to 125.8% and 16.2% as the number of cores increases and the clock frequency increases, respectively. However, note that the improvement of the GPU performance is saturated even though the number of cores increases and the clock frequency increases continuously, since the data cannot be provided to the GPU due to the limit of memory bandwidth. Consequently, to accomplish high performance effectiveness on GPU, computational resources must be more suitably considered.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.4
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• pp.37-47
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• 2016

The practical constraints on the commercial FPGAs which contain dedicated wide function multiplexers in their slice structure are incorporated with one of the most advanced FPGA mapping algorithms based on the AIG (And-Inverter Graph), one of the best logic representations in academia. As the first step of the mapping process, cuts are enumerated as intermediate structures. And then, the cuts which can be mapped to the multiplexers are recognized. Without any increased complexity, the delay and area of multiplexers as well as LUTs are calculated after checking the requirements for the tree construction such as symmetry and depth limit against dynamically changing mapping of neighboring nodes. Besides, the root positions of multiplexer trees are identified from the RTL code, and annotated to the AIG as AOs (Auxiliary Outputs). A new AIG embedding the multiplexer tree structures which are intentionally synthesized by Shannon expansion at the AOs, is overlapped with the optimized AIG. The lossless synthesis technique which employs FRAIG (Functionally Reduced AIG) is applied to this approach. The proposed approach and techniques are validated by implementing and applying them to two RISC processor examples, which yielded 13~30% area reduction, and up to 32% delay reduction. The research will be extended to take into account the constraints on the dedicated hardware for carry chains.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.4
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• pp.15-25
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• 2012

The research on the FPGA CAD tools in academia has been lacking practicality due to the underlying FPGA fabric architecture which is too simple and inefficient to be applied for commercial FPGAs. Recently, the database of placement positions and routing graphs on commercial FPGA architectures has been built, and provided for enabling the academic development of placement and routing tools. To extend the limit of academic CAD tools even further, we have developed the evaluation toolkit for the K-FPGA architecture which is under development. By providing interface for exchanging data with a commercial FPGA toolkit at every step of mapping, packing, placement and routing in the tool chain, the toolkit enables individual tools to be developed without waiting for the results of the preceding step, and with no dependency on the quality of the results, and compared in detail with commercial tools at any step. Also, the fabric primitive library is developed by extracting the prototype from a reporting file of a commercial FPGA, restructuring it, and modeling the behavior of basic gates. This library can be used as the benchmarking target, and a reference design for new FPGA architectures. Since the architecture is described in a standard HDL which is familiar with hardware designers, and read in the tools rather than hard coded, the tools are "data-driven", and tolerable with the architectural changes due to the design space exploration. The experiments confirm that the developed library is correct, and the functional correctness of applications implemented on the FPGA fabric can be validated by simulation. The placement and routing tools are under development. The completion of the toolkit will enable the development of practical FPGA architectures which, in return, will synergically animate the research on optimization CAD tools.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.455-458
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• 2013

The conventional design of the information system architecture based on the personal experience of information systems has been acted as a limit in progress utilizing appropriate resource allocation and performance improvements. Architecture design depending on personal experience makes differences in variance of a designer's experience, intellectual level in related tasks and surroundings, and architecture quality according to individual's propensity. After all these problems cause a waste of expensive hardware resources. At working place, post-monitoring tools are diversely developed and are running to find the bottleneck and the process problems in the information operation. However, there are no simulation tools or models that are used for expecting and counteracting the problems at early period of designing architecture. To solve these problems we will first develop a simulation model for designing information system architecture in a pilot form, and will verify validity. If an error rate is found in the permissible range, then it can be said that the simulation reflects the characteristic of information system architecture. After the model is developed in a level that can be used in various ways, more accurate performance computation will be able to do, getting out of the old way relying on calculations, and prevent the existence of idle resources and expense waste that comes from the wrong design of architecture.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.2B
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• pp.100-107
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• 2007

Recently, a study of BcN(Broadband convergence Network) is progressing continuously, and it is important to improve the quality of the service according to subscribers because a scale of network is about to be larger. It is more important to manage QoS(Quality of Service) of all subscribers in layer 2 than layer 3 network since managing it in layer 3 network cost both additional processes and large hardware. Moreover, QoS based on Best-Effort service has been developed because tots of subscribers should use limited resource in BcN. However, they want to be supplied with different service even though they pay more charge. Therefore, it is essential to assign the different bandwidth to subscribers depending on their level of charge. The method of current Rate Limiter limits the bandwidth of each port that does not offer fair service to subscribers. The Rate Limiter proposed in this paper limits bandwidth according to each subscriber. Therefore, subscribers can get fair service regardless of switch structure. This new Rate Limiter controls the bandwidth of subscribers according to the information of learning subscriber and manages maximum performance of Ethernet switch and QoS.