• International Journal of Control, Automation, and Systems
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• 제4권5호
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• pp.567-574
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• 2006

This paper presents the hardware implementation of a neural network controller for a nonlinear system with a micro-controller unit (MCU) and a field programmable gate array (FPGA) chip. As an on-line learning algorithm of a neural network, the reference compensation technique has been implemented on an MCU, while PID controllers with other functions such as counters and PWM generators are implemented on an FPGA chip. Interface between an MCU and a field programmable gate array (FPGA) chip has been developed to complete hardware implementation of a neural controller. The developed neural control hardware has been tested for balancing the inverted pendulum while controlling a desired trajectory of a cart as a nonlinear system.

• 한국전자통신학회논문지
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• 제5권2호
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• pp.158-163
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• 2010

본 연구에서는 Chua 회로의 선형 요소인 R, L C 성분의 요소 중에서 포화 특성을 가지고 있어 상용화된 제품으로는 제작 구현이 어려운 L 성분을 C 성분으로 대체하는 간략화한 Chua's 회로를 실제 하드웨어를 이용하여 제작하고 그 결과로 얻은 생성된 카오스 어트랙터를 기존의 Chua's 회로와 비교하였다.

• Nuclear Engineering and Technology
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• 제53권2호
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• pp.688-694
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• 2021

The aim of this work is the analysis, design and hardware implementation of the fractional-order point kinetics (FNPK) model along with its closed-loop controller. The stability and closed-loop control of FNPK models are critical issues. The closed-loop stability of the controller-plant structure is established. Further, the designed PI/PD controllers are implemented in real-time on a DSP processor. The simulation and real-time hardware studies confirm that the designed PI/PD controllers result in a damped stable closed-loop response.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2000년도 전력전자학술대회 논문집
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• pp.38-40
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• 2000

In this paper we propose a calculation method for fuzzy control based on quantized $\alpha$-cut decomposition of fuzzy sets. This method is easy to be implemented in analog hardware. The effect of quantization levels on defuzzified fuzzy inference results is investigated. A few quantization levels are sufficient for fuzzy control. The hardware implementation of this calculation method and the defuzzification by gravity center method by PWM are also presented.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2001년도 ICCAS
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• pp.131.1-131
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• 2001

At the present time, multimedia chip, internet application, and network equipment is designed by using ARM core. Because it has a good debugging, software compiler and needed low power. We must process a data coding to send a multimedia data by real time. So need to connect software and hardware algorithm. In this research, We design interface for ARM9/AMBA based board using VHDL for these function implementation. The board is used the ARM company´s ARM940T for software function implementation and Xilinx company´s Virtex E2000 for hardware function algorithm. The various hardware algorithm (ME,ME,DCT) block for performance can be implemented on this system.

• 융합신호처리학회 학술대회논문집
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• 한국신호처리시스템학회 2001년도 하계 학술대회 논문집(KISPS SUMMER CONFERENCE 2001
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• pp.133-136
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• 2001

In this paper, we propose a calculation method for fuzzy control based on quantized $\alpha$ -cut decomposition of fuzzy sets. This method is easy to be implemented in analog hardware. The effect of quantization levels on defuzzified fuzzy inference result is investigated. A few quantization levels are sufficient for fuzzy control. The hardware implementation of this calculation method and the defuzzificaion by gravity center method by PWM are also presented.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.281-284
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• 2002

Rijndael algorithm is known to a new private key block cipher which is substitute for DES. Rijndael algorithm is adequate to both hardware and software implementation, so hardware implementation of Rijndael algorithm is applied to high speed data encryption and decryption. This paper describes three implementation methods of Rijndael S-box, which is important factor in performance of Rijndael coprocessor. It shows synthesis results of each S-box implementation in Xilinx FPGA. Tllc lilree S-box implementation methods are implementation using lookup table only, implementation using both lookup table and combinational logic, and implementation using combinational logic only.

• 대한전기학회논문지
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• 제45권3호
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• pp.444-450
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• 1996

A digital hardware architecture for artificial neural network with learning capability is described in this paper. It is a modified hardware architecture known as HANNIBAL(Hardware Architecture for Neural Networks Implementing Back propagation Algorithm Learning). For implementing an efficient neural network hardware, we analyzed various type of multiplier which is major function block of neuro-processor cell. With this result, we design a efficient digital neural network hardware using serial/parallel multiplier, and test the operation. We also analyze the hardware efficiency with logic level simulation. (author). refs., figs., tabs.

• Journal of Power Electronics
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• 제16권2호
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• pp.553-563
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• 2016

This paper presents a digital hardware implementation of a real-time simulator for a multiphase drive using a field-programmable gate array (FPGA) device. The simulator was developed with a modular and hierarchical design using very high-speed integrated circuit hardware description language (VHDL). Hence, this simulator is flexible and portable. A state-space representation model suitable for FPGA implementations was proposed for a dual three-phase induction machine (DTPIM). The simulator also models a two-level 12-pulse insulated-gate bipolar transistor (IGBT)-based voltage-source converter (VSC), a pulse-width modulation scheme, and a measurement system. Real-time simulation outputs (stator currents and rotor speed) were validated under steady-state and transient conditions using as reference an experimental test bench based on a DTPIM with 15 kW-rated power. The accuracy of the proposed digital hardware implementation was evaluated according to the simulation and experimental results. Finally, statistical performance parameters were provided to analyze the efficiency of the proposed DTPIM hardware implementation method.

• 전기전자학회논문지
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• 제25권1호
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• pp.10-14
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• 2021

본 논문에서는 기존 CIE1931 색 좌표계를 이용한 색상 보정 연산의 복잡성을 개선한 하드웨어를 제안한다. 기존 알고리즘은 연산 과정에서 큰 비트 수를 계산하기 위해 사용되는 4-Split Multiply 연산으로 인해 하드웨어가 커지는 단점이 있다. 제안하는 알고리즘은 기존 알고리즘의 정의된 R2X, X2R 연산을 미리 계산하여 하나의 행렬로 만들어 영상에 적용함으로써 연산량 감소와 하드웨어 크기 감소가 가능하다. Verilog로 설계된 하드웨어의 Xilinx 합성 결과를 비교함으로써 하드웨어 자원 감소와 4K 환경 실시간 처리를 위한 성능을 확인할 수 있다. 또한, FPGA 보드에서의 실행 결과를 제시함으로써 하드웨어 탑재 동작을 검증하였다.