• International Journal of Control, Automation, and Systems
• /
• v.4 no.5
• /
• pp.567-574
• /
• 2006

This paper presents the hardware implementation of a neural network controller for a nonlinear system with a micro-controller unit (MCU) and a field programmable gate array (FPGA) chip. As an on-line learning algorithm of a neural network, the reference compensation technique has been implemented on an MCU, while PID controllers with other functions such as counters and PWM generators are implemented on an FPGA chip. Interface between an MCU and a field programmable gate array (FPGA) chip has been developed to complete hardware implementation of a neural controller. The developed neural control hardware has been tested for balancing the inverted pendulum while controlling a desired trajectory of a cart as a nonlinear system.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.5 no.2
• /
• pp.158-163
• /
• 2010

In this paper, we implemened the simplified Chua's circuit which is replace L to C by real hardware implementation. Because L element has a difficult problem to make a real hardware, L has a saturation characteristic and we also compare with previous Chua's circuit as the result of chaostic attractors creation.

• Nuclear Engineering and Technology
• /
• v.53 no.2
• /
• pp.688-694
• /
• 2021

The aim of this work is the analysis, design and hardware implementation of the fractional-order point kinetics (FNPK) model along with its closed-loop controller. The stability and closed-loop control of FNPK models are critical issues. The closed-loop stability of the controller-plant structure is established. Further, the designed PI/PD controllers are implemented in real-time on a DSP processor. The simulation and real-time hardware studies confirm that the designed PI/PD controllers result in a damped stable closed-loop response.

• Proceedings of the KIPE Conference
• /
• 2000.07a
• /
• pp.38-40
• /
• 2000

In this paper we propose a calculation method for fuzzy control based on quantized $\alpha$-cut decomposition of fuzzy sets. This method is easy to be implemented in analog hardware. The effect of quantization levels on defuzzified fuzzy inference results is investigated. A few quantization levels are sufficient for fuzzy control. The hardware implementation of this calculation method and the defuzzification by gravity center method by PWM are also presented.

• 제어로봇시스템학회:학술대회논문집
• /
• 2001.10a
• /
• pp.131.1-131
• /
• 2001

At the present time, multimedia chip, internet application, and network equipment is designed by using ARM core. Because it has a good debugging, software compiler and needed low power. We must process a data coding to send a multimedia data by real time. So need to connect software and hardware algorithm. In this research, We design interface for ARM9/AMBA based board using VHDL for these function implementation. The board is used the ARM company´s ARM940T for software function implementation and Xilinx company´s Virtex E2000 for hardware function algorithm. The various hardware algorithm (ME,ME,DCT) block for performance can be implemented on this system.

• Proceedings of the Korea Institute of Convergence Signal Processing
• /
• 2001.06a
• /
• pp.133-136
• /
• 2001

In this paper, we propose a calculation method for fuzzy control based on quantized $\alpha$ -cut decomposition of fuzzy sets. This method is easy to be implemented in analog hardware. The effect of quantization levels on defuzzified fuzzy inference result is investigated. A few quantization levels are sufficient for fuzzy control. The hardware implementation of this calculation method and the defuzzificaion by gravity center method by PWM are also presented.

• Proceedings of the IEEK Conference
• /
• 2002.06b
• /
• pp.281-284
• /
• 2002

Rijndael algorithm is known to a new private key block cipher which is substitute for DES. Rijndael algorithm is adequate to both hardware and software implementation, so hardware implementation of Rijndael algorithm is applied to high speed data encryption and decryption. This paper describes three implementation methods of Rijndael S-box, which is important factor in performance of Rijndael coprocessor. It shows synthesis results of each S-box implementation in Xilinx FPGA. Tllc lilree S-box implementation methods are implementation using lookup table only, implementation using both lookup table and combinational logic, and implementation using combinational logic only.

• The Transactions of the Korean Institute of Electrical Engineers
• /
• v.45 no.3
• /
• pp.444-450
• /
• 1996

A digital hardware architecture for artificial neural network with learning capability is described in this paper. It is a modified hardware architecture known as HANNIBAL(Hardware Architecture for Neural Networks Implementing Back propagation Algorithm Learning). For implementing an efficient neural network hardware, we analyzed various type of multiplier which is major function block of neuro-processor cell. With this result, we design a efficient digital neural network hardware using serial/parallel multiplier, and test the operation. We also analyze the hardware efficiency with logic level simulation. (author). refs., figs., tabs.

• Journal of Power Electronics
• /
• v.16 no.2
• /
• pp.553-563
• /
• 2016

This paper presents a digital hardware implementation of a real-time simulator for a multiphase drive using a field-programmable gate array (FPGA) device. The simulator was developed with a modular and hierarchical design using very high-speed integrated circuit hardware description language (VHDL). Hence, this simulator is flexible and portable. A state-space representation model suitable for FPGA implementations was proposed for a dual three-phase induction machine (DTPIM). The simulator also models a two-level 12-pulse insulated-gate bipolar transistor (IGBT)-based voltage-source converter (VSC), a pulse-width modulation scheme, and a measurement system. Real-time simulation outputs (stator currents and rotor speed) were validated under steady-state and transient conditions using as reference an experimental test bench based on a DTPIM with 15 kW-rated power. The accuracy of the proposed digital hardware implementation was evaluated according to the simulation and experimental results. Finally, statistical performance parameters were provided to analyze the efficiency of the proposed DTPIM hardware implementation method.

• Journal of IKEEE
• /
• v.25 no.1
• /
• pp.10-14
• /
• 2021

This paper presents a hardware that improves the complexity of the CIE1931 color coordinate algorithm operation. The conventional algorithm has disadvantage of growing hardware due to 4-Split Multiply operations used to calculate large bits in the computation process. But the proposed algorithm pre-calculates the defined R2X, X2R Matrix operations of the conventional algorithm and makes them a matrix. By applying the matrix to the images and improving the color, it is possible to reduce the amount of computation and hardware size. By comparing the results of Xilinx synthesis of hardware designed with Verilog, we can check the performance for real-time processing in 4K environments with reduced hardware resources. Furthermore, this paper validates the hardware mount behavior by presenting the execution results of the FPGA board.