• JSTS:Journal of Semiconductor Technology and Science
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• 제16권1호
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• pp.118-125
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• 2016

This paper presents a new high-efficient algorithm and architecture for an elliptic curve cryptographic processor. To reduce the computational complexity, novel modified Lopez-Dahab scalar point multiplication and left-to-right algorithms are proposed for point multiplication operation. Moreover, bit-serial Galois-field multiplication is used in order to decrease hardware complexity. The field multiplication operations are performed in parallel to improve system latency. As a result, our approach can reduce hardware costs, while the total time required for point multiplication is kept to a reasonable amount. The results on a Xilinx Virtex-5, Virtex-7 FPGAs and VLSI implementation show that the proposed architecture has less hardware complexity, number of clock cycles and higher efficiency than the previous works.

• JSTS:Journal of Semiconductor Technology and Science
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• 제3권4호
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• pp.199-204
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• 2003

This paper proposes reconfigurable hardware structures for spreading and scrambling of multi-mode CDMA systems. The proposed reconfigurable structures supporting IS-95, cdma2000 and WCDMA, include a pseudo noise code generator, a channelization code generator and a control circuit for signal flow control. The proposed reconfigurable structures provide an efficient hardware usage for multi-mode CDMA systems. The synthesis results show the area reduction about 24.7% compared with the original code generators. The proposed structures can provide efficient reconfigurability and high speed operations for future SDR systems.

• 한국통신학회논문지
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• 제25권10B호
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• pp.1793-1802
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• 2000

In this paper we propose an efficient implementation technique for cyclic extension in VDSL(Very High bit-rate Digital Subscriber Line) systems using Zipper duplexing and analyze its performances under typical telephone channel environments. In Zipper-based VDSL systems each DTM(discrete-multitone) block is appended by both cyclic prefix(CP) and cyclic suffix(CS). The CP is inserte to prevent both intersymbol interference (ISI) and iterchannel interference (ICI) while the CS is appended to ensure orthogonality between the upstream and downstream carriers thus preventing near-end crosstalk (NEXT). However in order to implement the CP in the transmitter side of the VDSL system an additional hardware is required to append the latter part of each DMT symbol to the beginning of the DMT symbol. In this paper we propose a VDSL system with Zipper duplexing using only CS to reduce hardware complexity (memory and processing delay) required for implementation of CP. It is shown by computer simulation that the proposed approach has the same capacity under typical channel environments as the previous Zipper-based VDSL system using both CP and CS. even with a significantly lower hardware complexity.

• Journal of information and communication convergence engineering
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• 제11권2호
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• pp.118-123
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• 2013

This paper proposes an efficient hardware architecture for high efficiency video coding (HEVC), which is the next generation video compression standard. It adopts several new coding techniques to reduce the bit rate by about 50% compared with the previous one. Unlike the previous H.264/AVC 6-tap interpolation filter, in HEVC, a one-dimensional seven-tap and eight-tap filter is adopted for luma interpolation, but it also increases the complexity and gate area in hardware implementation. In this paper, we propose a parallel architecture to boost the interpolation performance, achieving a luma $4{\times}4$ block interpolation in 2-4 cycles. The proposed architecture contains shared operations reducing the gate count increased due to the parallel architecture. This makes the area efficiency better than the previous design, in the best case, with the performance improved by about 75.15%. It is synthesized with the MagnaChip $0.18{\mu}m$ library and can reach the maximum frequency of 200 MHz.

• 디지털산업정보학회논문지
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• 제18권1호
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• pp.1-9
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• 2022

Galois field arithmetic is important in error correcting codes and public-key cryptography schemes. Hardware realization of these schemes requires an efficient implementation of Galois field arithmetic operations. Multiplication is the main finite field operation and designing efficient multiplier can clearly affect the performance of compute-intensive applications. Diverse algorithms and hardware architectures are presented in the literature for hardware realization of Galois field multiplication to acquire a reduction in time and area. This paper presents a low complexity semi-systolic multiplier to facilitate parallel processing by partitioning Montgomery modular multiplication (MMM) into two independent and identical units and two-level systolic computation scheme. Analytical results indicate that the proposed multiplier achieves lower area-time (AT) complexity compared to related multipliers. Moreover, the proposed method has regularity, concurrency, and modularity, and thus is well suited for VLSI implementation. It can be applied as a core circuit for multiplication and division/exponentiation.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2011년도 춘계학술대회
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• pp.643-645
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• 2011

We analysed a hardware design issues, which is strong, compact and efficient. Due to its low area constraints, primitive based on hardware is especially suited for RFID (Radio Frequency Identification) devices. primitive is based on the classical DES (Data Encryption Standard) design. This approach makes it possible to considerably decrease chip size requirements.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권3호
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• pp.425-437
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• 2017

For efficient hardware (HW) implementation of elliptic curve cryptography (ECC), various sub-modules for the underlying finite field operations should be implemented efficiently. Among these sub-modules, modular inversion (MI) requires the most computation; therefore, its performance might be a dominant factor of the overall performance of an ECC module. To determine the most efficient MI algorithm for an HW ECC module, we implement various classes of MI algorithms and analyze their performance. In contrast to the common belief in previous research, our results show that the right-shift binary inversion (RS) algorithm performs well when implemented in hardware. In addition, we present optimization methods to reduce the area overhead and improve the speed of the RS algorithm. By applying these methods, we propose a new RS-variant that is both fast and compact. The proposed MI module is more than twice as fast as the other two classes of MI: shifting Euclidean (SE) and left-shift binary inversion (LS) algorithms. It consumes only 15% more area and even 5% less area than SE and LS, respectively. Finally, we show that how our new method can be applied to optimize an HW ECC module.

• 한국정보통신학회논문지
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• 제19권4호
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• pp.888-894
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• 2015

국가보안기술연구소(NSRI)에서 개발된 경량 블록암호 알고리듬 LEA(Lightweight Encryption Algorithm)의 효율적인 하드웨어 설계에 대해 기술한다. 마스터키 길이 128비트를 지원하도록 설계되었으며, 라운드 변환블록과 키 스케줄러의 암호화 연산과 복호화 연산을 위한 하드웨어 자원이 공유되도록 설계하여 저전력, 저면적 구현을 실현했다. 설계된 LEA 프로세서는 FPGA 구현을 통해 하드웨어 동작을 검증하였다. Xilinx ISE를 이용한 합성결과 LEA 코어는 1,498 슬라이스로 구현되었으며, 135.15 MHz로 동작하여 216.24 Mbps의 성능을 갖는 것으로 평가 되었다.

• ETRI Journal
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• 제25권5호
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• pp.328-336
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• 2003

Bluetooth is a specification for short-range wireless communication using the 2.4 GHz ISM band. It emphasizes low complexity, low power, and low cost. This paper describes an area-efficient digital baseband module for wireless technology. For area-efficiency, we carefully consider hardware and software partitioning. We implement complex control tasks of the Bluetooth baseband layer protocols in software running on an embedded microcontroller. Hardware-efficient functions, such as low-level bitstream link control; host controller interfaces (HCIs), such as universal asynchronous receiver transmitter (UART) and universal serial bus (USB)interfaces; and audio Codec are performed by dedicated hardware blocks. Furthermore, we eliminate FIFOs for data buffering between hardware functional units. The design is done using fully synthesizable Verilog HDL to enhance the portability between process technologies so that our module can be easily integrated as an intellectual property core no system-on-a-chip (SoC) ASICs. A field programmable gate array (FPGA) prototype of this module was tested for functional verification and realtime operation of file and bitstream transfers between PCs. The module was fabricated in a $0.25-{\mu}m$ CMOS technology, the core size of which was only 2.79 $mm{\times}2.80mm$.

• 한국CDE학회논문집
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• 제15권2호
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• pp.115-123
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• 2010

We present an efficient algorithm for computing the Hausdorff distance between two planar curves. The algorithm is based on an efficient trimming technique that eliminates the curve domains that make no contribution to the final Hausdorff distance. The input curves are first approximated with biarcs within a given error bound in a pre-processing step. Using the biarc approximation, the distance map of an input curve is then approximated and stored into the graphics hardware depth-buffer by rendering the distance maps (represented as circular cones) of the biarcs. We repeat the same procedure for the other input curve. By sampling points on each input curve and reading the distance from the other curve (stored in the hardware depth-buffer), we can easily estimate a lower bound of the Hausdorff distance. Based on the lower bound, the algorithm eliminates redundant curve segments where the exact Hausdorff distance can never be obtained. Finally, we employ a multivariate equation solver to compute the Hausdorff distance efficiently using the remaining curve segments only.