• 정보보호학회논문지
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• 제29권4호
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• pp.739-751
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• 2019

임베디드 기기의 보안성이 주요한 문제로 부상하고 있다. 관련된 문제 중 특히 공급망 공격은 국가 간의 분쟁으로 이어질 수 있어 심각한 문제로 대두되고 있다. 공급망 공격을 완화하기 위하여 하드웨어 구성요소, 특히 AES와 같은 암호 모듈에 대한 CC(Common Criteria) EAL(Evaluation Assurance Level) 5 이상 고등급 보안성 인증 및 평가가 필요하다. 고등급 보안성 인증 및 평가를 위하여 암호 모듈에 대한 은닉 채널, 즉 백도어를 탐지하는 것이 필요하다. 그러나 기존의 연구로는 암호 모듈 그 중 AES의 비밀 키를 복구시킬 수 있는 정보가 유출되는 백도어를 탐지하지 못하는 한계가 있다. 따라서 본 논문은 기존의 하드웨어 AES 모듈 백도어의 정의를 확장하여 개선시킨 새로운 정의를 제안하고자 한다. 또한, 이 정의를 이용하여 기존 연구가 탐지하지 못했던 백도어를 탐색하는 과정을 제시한다. 이 탐색 과정은 Verilog HDL (Hardware Description Language)로 표현된 AES 모듈을 정형 기법 도구인 모델 체커(Model Checker) NuSMV를 이용하여 검증하는 것으로 백도어를 탐색한다.

• 전자공학회논문지C
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• 제35C권5호
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• pp.1-10
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• 1998

In this paper, a new hardware-software patitioning algorithm is presented, in which the system behavioral description containing a mixture of hardware and softwae components is partitioned into the hardware part and the software part. In this research, new techniques to optimally partition a mixed system under certain specified constaints such as performance, area, and delay, have been developed. During the partitioning process, the overhead due to the communication between the hardware and software parts are considered. New featues have been added to adjust the hierarchical level of partitioning. Power consumption, memory cost, and the effect of pipelining can also be considered during partitioning. Another new feature is the ability to partition a DSP system under throughput constraints. This feature is important for real time processing. The developed partitioning system can also be used to evaluate various design alternatives and architectures.

• Journal of Positioning, Navigation, and Timing
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• 제13권2호
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• pp.149-158
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• 2024

Global Navigation Satellite System (GNSS) receivers are becoming increasingly sophisticated, equipped with advanced features and precise specifications, thus demanding efficient and high-performance hardware platforms. This paper presents the design and implementation of a Field-Programmable Gate Array (FPGA)-based GNSS receiver development platform for multi-band signal processing. This platform utilizes a FPGA to provide a flexible and re-configurable hardware environment, enabling real-time signal processing, position determination, and handling of large-scale data. Integrated signal processing of L/S bands enhances the performance and functionality of GNSS receivers. Key components such as the RF frontend, signal processing modules, and power management are designed to ensure optimal signal reception and processing, supporting multiple GNSS. The developed hardware platform enables real-time signal processing and position determination, supporting multiple GNSS systems, thereby contributing to the advancement of GNSS development and research.

• ETRI Journal
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• 제30권1호
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• pp.141-151
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• 2008

In this paper, we introduce a new verification platform with ARM- and DSP-based multiprocessor architecture. Its simple communication interface with a crossbar switch architecture is suitable for a heterogeneous multiprocessor platform. The platform is used to verify the function and performance of a DVB-T baseband receiver using hardware and software partitioning techniques with a seamless hardware/software co-verification tool. We present a dual-processor platform with an ARM926 and a Teak DSP, but it cannot satisfy the standard specification of EN 300 744 of DVB-T ETSI. Therefore, we propose a new multiprocessor strategy with an ARM926 and three Teak DSPs synchronized at 166 MHz to satisfy the required specification of DVB-T.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1993년도 한국자동제어학술회의논문집(국내학술편); Seoul National University, Seoul; 20-22 Oct. 1993
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• pp.788-792
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• 1993

The objective of this study is to develope a satellite dynamic simulator, which can test and analyze the performance of spacecraft attitude control, antenna pointing instruments, communication equipments and spacecraft components under the space environment. The satellite simulator can be used to predict the events such as malfunction and failure of satellites in space during operation and can be used to protect against emergencies. At first, the performance test system of attitude control is investigated which can simulate motion and verify stability of spacecraft. Our system consists of an attitude control main processor and a sub-processor including some real hardwares such as attitude sensors and actuators. In this paper, we describe the procedure of designing and manufacturing the dynamic simulator hardware, which consists of the central processor board, the sub-processor board and the sun sensor, and also communication between the components.

• 전기전자학회논문지
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• 제12권2호
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• pp.75-80
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• 2008

There are many researches to reduce power consumption of battery-operated Transceiver for 2.4 GHz smartRF applications. However, components such as processor, memory and LCD based power managements reach the limit of reducing power consumption. To overcome the limit, this research proposes novel low-power Transceiver and transceiver Hardware Design. Experimental results in the real smartRF Transceiver show that the proposed methods can reduce power consumption additionally than component based power managements.

• Journal of Information Processing Systems
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• 제8권1호
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• pp.101-118
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• 2012

Embedded products are becoming richer in features. Simulation tools facilitate low-costs and the efficient development of embedded systems. SID is an open source simulation software that includes a library of components for modeling hardware and software components. SID components were originally written using C/C++ and Tcl/Tk. Tcl/Tk has mainly been used for GUI simulation in the SID system. However, Tcl/Tk components are hampered by low performance, and GUI development using Tcl/Tk also has poor flexibility. Therefore, it would be desirable to use a more advanced programming language, such as Java, to provide simulations of cutting-edge products with rich graphics. Here, we describe the development of the Java Bridge Module as a middleware that will enable the use of Java Components in SID. We also extended the low-level SID API to Java. In addition, we have added classes that contain default implementations of the API. These classes are intended to ensure the compatibility and simplicity of SID components in Java.

• 인터넷정보학회논문지
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• 제21권2호
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• pp.109-119
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• 2020

FPGA는 초기 제작 후 다시 설계 할 수 있는 반도체로 신호 처리, 자동차 산업, 국방 및 군사 시스템 등과 같은 다양한 임베디드 시스템 분야에서 사용된다. 하지만 하드웨어 설계의 복잡성이 증가하고 설계 및 제조 과정이 세계화됨에 따라 하드웨어에 삽입되는 하드웨어 악성기능에 대한 우려가 커져가고 있다. 이러한 위협에 대응하기 위해 많은 탐지 방법들이 제시되었지만, 기존 방법 대부분은 IC칩을 대상으로 하고 있어 IC칩과 구성요소가 다른 FPGA에 적용하기 어렵다. 또한 FPGA 칩을 대상으로 하는 하드웨어 악성기능탐지 연구는 거의 이루어지지 않고 있다. 본 논문에서는 이러한 문제점을 해결하기 위해 FPGA의 LUT-level netlist에서 나타나는 하드웨어 악성기능의 정적인 특징을 기계학습을 통해 학습하여 하드웨어 악성기능을 탐지하는 방법을 제시한다.

• 전기학회논문지
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• 제66권9호
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• pp.1373-1378
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• 2017

This paper presents a basic ECU(Electronic Control Unit) hardware development procedure for the functional safety of in-vehicle network systems. We consider complete hardware redundancy as a safety mechanism for in-vehicle communication network under the assumption of the wired network failure such as disconnection of a CAN bus. An ESC (Electronic Stability Control) system is selected as an item and the required ASIL(Automotive Safety Integrity Level) for this item is assigned by performing the HARA(Hazard Analysis and Risk Assessment). The basic hardware architecture of the ESC system is designed with a microcontroller, passive components, and communication transceivers. The required ASIL for ESC system is shown to be satisfied with the designed safety mechanism by calculation of hardware architecture metrics such as the SPFM(Single Point Fault Metric) and the LFM(Latent Fault Metric).

• 한국정보처리학회:학술대회논문집
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• 한국정보처리학회 2010년도 추계학술발표대회
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• pp.1635-1637
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• 2010

Simulation tools help creating a low cost and efficient development of embedded system. SID is an open source simulator software that consists library of components for modelling hardware and software components. A component can be written in C/C++ and Tcl/Tk. Currently, the SID simulation toolkit only provides support for C++ and Tcl/Tk. Tcl/Tk is used to write GUI-based components. However, we have observed that Tcl/Tk components cause slow simulation response because Tcl/Tk is a script language. It is not proper for developing the cutting-edge products with rich graphics. Therefore, in this paper, we suggest Java to a new language for GUI components in SID by developing a bridge module for SID to interworking with Java components.