• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.3A
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• pp.237-246
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• 2007

Clock Synchronization is one of the most basic factors to be considered when we implement an indoor synchronization network for indoor positioning. In this paper, we present a new synchronization algorithm which does not employ time stamps in order to reduce the hardware complexity and data overhead. In addition to that, we describe an algorithm that is designed to compensate the frequency drift giving an serious impact on the synchronization performance. The performance evaluation of the proposed algorithm is achieved by investigating MTIE (Maximum Time Interval Error) values through simulations. In the simulations, the frequency drift values of the practical oscillators are used. From the simulation results, it is investigated that we can achieve the synchronization performance under 10 ns when we use 1 second synchronization interval with 1 ns resolution and TCXOs (Tmperature Compensated Cristal Oscillators) both in the master clock and the slave clock.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.1
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• pp.38-46
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• 1992

In this thesis, a high speed code synchronization circuit is implemented, which is applicable to frequency hopping FSK tranceiver within 68-88 MIBz band- width. synchronization Process consists of two steps, initial synchronization and tracking. A modified matched filter method using two channel passive correlators matched with short hopping frequencies, synchronization prcfix. is proposed for initial synchronization. To increase probability of initial synchronization, prefix are transmitted repeatedly. The outputs of correlators are sent to synchronization decision circuit, and code start time Is extracted by synchronizatlon decision circuit-Modified matched fitter method makes it possible to reduce complexity in hardware and obtain code acquisition rapidly.Clock recovery circuit regenerates PN code clock for tracking.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.2
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• pp.165-176
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• 2015

Clock or time synchronization protocol is one of the crucial factors that could determine the quality of the communication. With the rapid development of the network technology, more robust clock synchronization algorithm is required. IEEE 1588 is one of the possible solutions for a robust clock synchronization algorithm; however, there are still some challenges that need to be concerned in IEEE 1588 in term of reducing and stabilizing the PDV value. This survey paper shows several solutions that could improve the performance of IEEE 1588, including modifying the PTP message transmission, optimizing PTP method, filtering techniques, and using the hardware timestamp instead of application layer timestamp, and so on. Despite the improvement that is created with these techniques, the clock synchronization algorithm is still an open issue in the network communication.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.5
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• pp.1045-1057
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• 1997

In this paper, we propose an algorithm of block synchronization that uses data withoug synchronization preambles. Block synchronization systems is implemented using the DSP chip employing the proposed algorithm. The data spread of the DFT blocks is proportional to the offset of DFT block and this information is used to achieve the block synchronization in the receiver. The initial bleock synchronization and the clock synchronization between transmitter and receiver are achieved using the early-late removal of the guard interval. The hardware implmentation is carried out using the DSP chip TM320C30 to verify the proposed block synchronization algorithm with the data rate 1200bps. The DSP chip calculates the spread of the 128 complex FFT in the receiver with the system clock 30MHz. It is believed that the proposed synchronization algorithm can be used in the design of OFDM block synchronization with the high processing DSP chip.

• Journal of Satellite, Information and Communications
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• v.10 no.1
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• pp.71-76
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• 2015

In this paper, we developed the hardware GPS signal generator for generating a satellite navigation signal synchronized with Live GPS signal signals and analyzed the performance of signal genterator thorough the experiment For a hardware implementation of the GPS navigation signal synchronous generator, the GPS module may receive a GPS signal in order to generate the same signal as the operation that is transmitted from the current GPS satellite and the synchronized time information and the GPS satellites using the Novatel Inc. OEMStar.In. For generating the GPS synchronization signal, the GPS navigation signal generator was adjusted to a reference clock using the GPS clock synchronous information provided by the GPS receiving module and GPS signals also generated in consideration of the delay of the internal hardware of the generator. In this paper, we analyzed the effect of the receiver via the signal switching between Live GPS signal and generates a signal to measure the performance of the GPS navigation synchronization signal generator. It was confirmed that by the seamless operation of the signal even the moment that the switching of the generated signal from Live GPS signal has occurred through experimentation.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.8
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• pp.859-866
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• 1988

A high speed frame synchronization system has been realized which generates the frame sync clock from 565Mb/s data stream (the DS-5 digital multiplex hierarchy signal). The design of a frame pattern detector using a parallel detection method brings into low speed operation and resolves the problems due to the high speed operation. The frame synchronization algorithm recommended by CCITT is also realized by designing a sync mode controller. Appropriate design procedures are considered for an efficient hardware design and minimized connection lines. The CAD simulation as well as experiment show that the performance of the newly designed frame synchronization system satisfies the relevant requirements.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.1B
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• pp.86-97
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• 2009

RTLS is a system for automatically locating and tracking people and objects. The TDOA-based RTLS determines the location of the tag by calculating the time differences of a signal received from the tag. In TDOA-based RTLS, time synchronization is essential to calculate the time difference between readers. This paper presents a precision time synchronization method for TDOA-based RTLS over IEEE 802.15.4. In order to achieve precision time synchronization in IEEE 802.15.4 radio, we analyzed the error factors of delay and jitter. We also deal with the implementation of hardware assisted time stamping and the Kalman filtering method to minimize the error factors. In addition, this paper described the experiments and performance evaluation of the proposed precision time synchronization method in IEEE 802.15.4 radio. The results show that the nodes in a network can maintain their clocks to within 10 nanoseconds offset from the reference clock.

• Aerospace Engineering and Technology
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• v.3 no.1
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• pp.109-116
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• 2004

In a satellite time management system, the GPS-based clock synchronization technique[1] has the merits of precision time management by knowing the time difference or the error between the OBT(On Board Time) of the internal processors and GPS time every second. It can be realized employing the DPLL(Digital Phase Loop Lock) and FEP(Front End Processor) circuitry for the clock synchronization[2]. In this paper, a refined DPLL & FEP scheme is proposed to provide the precision, stability and robustness of the operation, which is to compensate the errors and noise of the GPS signal, and also to cope with the case when the GPS signal is lost due to several reasons. The simulation and HIL (Hardware In the Loop) test results using the FM(Flight Model) in the course of KOMPSAT-2(Korea Multi Purpose Satellite-2) design and development are illustrated to demonstrate the salient features of this methodology.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.6
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• pp.446-455
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• 2001

In this paper, the precise synchronized clock generator using GPS receiver is presented. The GPS receiver provides a synchronized IPPS signal which guaranties a reliable standard time mark. This signal allows us to do time synchronization and correct the time step. We designed and implemented the precise synchronized clock generator based on DPLL in order to generate a high-resolution clock from a low-cost inaccurate oscillator with ALTERA FLEX EPM6016TC144-3. We also implemented a hardware unit and proved that the unit provides 1MHz clock output which had a high resolution and accuracy when it was combined with GPS receiver.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.716-719
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• 1999

In this paper, a real-time control system for robot manipulator is implemented using real-time operating system with capabilities of multitasking, intertask communication and synchronization, event-driven, priority-driven scheduling, real-time clock control, etc. The hardware system with VME bus and related devices is developed and applied to implement a dynamic learning control scheme for robot manipulator. Real-time performance of the proposed dynamic learning controller is tested for tasks of tracking moving objects and compared with the conventional servo controller.