• 한국정보처리학회:학술대회논문집
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• 한국정보처리학회 2009년도 추계학술발표대회
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• pp.67-68
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• 2009

Increasing use of embedded systems has made many improvements on hardware development for specific purpose. Hardware changes are more expensive and harder to implement rather than software changes. Developers need tools to do design and testing of new hardware. Many simulation tools have been made to mimic the hardware and allow developer to test programs on top of new hardware. Virtual Development Environment for Embedded Software (VDEES) is one of the alternatives available. It provides an open source based platform and an Integrated Development Environment (IDE) that can be used to build and testing newly made component, faster and at low-cost.

• 대한임베디드공학회논문지
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• 제7권1호
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• pp.17-24
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• 2012

Recently automotive software has been more complex and needs to be reduced its development time. Software testing of its functionalities and performance should be conducted in an early development phase to reduce time to market and the development cost. Software functional testing can be performed through simulating the hardware, but it is not guaranteed that evaluation of real-time performance using simulation has enough accuracy. Real-time performance can be precisely evaluated with hardware-in-the-loop simulation, but it costs time and effort to set up hardware for testing. In this paper, we suggest a testing system that can evaluate functional requirements and real time properties with a general-purpose development board in the early development phase. In addition, we improve reusability of the testing system through modularized and layered architecture. With the proposed testing system we can contribute to building reliable testing system at low cost without difficulty.

• 한국통신학회논문지
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• 제25권4B호
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• pp.771-782
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• 2000

이 논문에서는 하드웨어와 소프트웨어의 통합 설계에 의한 H.263 동영상 코덱을 구현한다. 동영상의 부호화와 복호화를 실시간으로 수행하기 위해 동작 속도 및 응용성을 동시에 고려하여 H.263 코덱의 각 부분 중 어느 부분이 하드웨어 또는 소프트웨어로 구현된는 것이 바람직한지 결정하였다. 하드웨어로 구현하는 부분은 움직임 추정부 및 보상부와 메모리 제어부이고, 나머지 부분은 RISC (reduced instruction set computer) 프로세서를 사용하여 소프트웨어로 처리한다. 이 논문에서는 하드웨어 및 소프트웨어 모듈의 효과적인 구현 방법을 소개한다. 특히 하드웨어로 구현되는 움직임 추정부를 위해서 주변 움직임 변위의 상관성 및 계층적 탐색을 이용한 다수의 움직임 후보를 가지고 알고리즘을 사용하였으며, 이 알고리즘에 기반한 소면적 구조를 제안한다. 소프트웨어로 처리되는 DCT (discrete cosine transform) 부분의 최적화를 위해서 움직임 추정부에서 얻어진 SAD (sum of absolute difference) 값에 근거하여 DCT 이후 양자화된 계수들의 통계적 특성을 분류하는 기법을 사용한다. 제안된 방법을 실제 RISC 프로세서와 gate array를 이용하여 구\ulcorner하고, 그 성능이 우수함을 확인하였다.

• 스마트미디어저널
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• 제5권4호
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• pp.49-56
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• 2016

무선인터넷이 보급되고 IoT 기술이 발달함에 따라 여러 종류의 센서 디바이스가 발전하였다. 그리고 IoT 환경에서 사용자들의 요구를 충족하는 다양한 서비스 개발을 위해 오픈소스 하드웨어가 도입되었다. 하지만 오픈소스 하드웨어는 개발 인력의 부족으로 인해 충분히 활용되지 못하고 있다. 따라서 본 논문에서는 오픈소스 하드웨어에서 효율적으로 임베디드 소프트웨어 개발을 교육하기 위한 소프트웨어 프레임워크를 제안한다. 제안하는 프레임워크는 비주얼 프로그래밍 언어와 빠른 결과 확인을 통해 다양한 오픈소스 하드웨어에서 빠르고 직관적으로 임베디드 소프트웨어를 개발할 수 있게 한다. 또한 제안한 프레임워크를 실제 오픈소스 하드웨어 개발 환경에 구현하여 장단점을 분석하고 개선방안을 확인하였다.

• 전자통신동향분석
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• 제36권6호
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• pp.78-87
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• 2021

Information technology (IT) has been applied to various fields, and currently, IT devices and systems are used in very important areas, such as aviation, industry, and national defense. Such devices and systems are subject to various types of malicious attacks, which can be software or hardware based. Compared to software-based attacks, hardware-based attacks are known to be much more difficult to detect. A hardware Trojan horse is a representative example of hardware-based attacks. A hardware Trojan horse attack inserts a circuit into an IC chip. The inserted circuit performs malicious actions, such as causing a system malfunction or leaking important information. This has increased the potential for attack in the current supply chain environment, which is jointly developed by various companies. In this paper, we discuss the future direction of research by introducing attack cases, the characteristics of hardware Trojan horses, and countermeasure trends.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제4권6호
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• pp.1294-1310
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• 2010

User authentication using fingerprint information provides convenience as well as strong security. However, serious problems may occur if fingerprint information stored for user authentication is used illegally by a different person since it cannot be changed freely as a password due to a limited number of fingers. Recently, research in fuzzy fingerprint vault system has been carried out actively to safely protect fingerprint information in a fingerprint authentication system. In addition, research to solve the fingerprint alignment problem by applying a geometric hashing technique has also been carried out. In this paper, we propose the hardware architecture for a geometric hashing based fuzzy fingerprint vault system that consists of the software module and hardware module. The hardware module performs the matching for the transformed minutiae in the enrollment hash table and verification hash table. On the other hand, the software module is responsible for hardware feature extraction. We also propose the hardware architecture which parallel processing technique is applied for high speed processing. Based on the experimental results, we confirmed that execution time for the proposed hardware architecture was 0.24 second when number of real minutiae was 36 and number of chaff minutiae was 200, whereas that of the software solution was 1.13 second. For the same condition, execution time of the hardware architecture which parallel processing technique was applied was 0.01 second. Note that the proposed hardware architecture can achieve a speed-up of close to 100 times compared to a software based solution.

• 한국멀티미디어학회논문지
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• 제21권2호
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• pp.261-270
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• 2018

Hearing-impaired people are increasing rapidly due to the global aging trend. Early detection of hearing loss requires an easy-to-use audiometry device for the public. Existing audiometry systems were developed as PC-based, PDA-based, or smartphone apps. These devices were often dependent on specific software platforms and hardware platforms. In this paper, we tried to improve software platform compatibility by using cross platform, and tried to implement IoT-based pure tone audiometry device which does not require sound pressure level correction due to hardware differences. Pure tone audiometry is available in a variety of ways depending on the type of hearing loss and age. Using the IoT-based audiometry device implemented in this paper, it will be possible for an app developer who lacks hardware knowledge to easily develop an app with various scenarios for hearing screening. The results of this study will contribute to overcoming the software and hardware dependency in the development of IoT-based healthcare device.

• 한국전산유체공학회:학술대회논문집
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• 한국전산유체공학회 2006년도 추계 학술대회논문집
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• pp.207-207
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• 2006

Hardware technologies for high-performance computing has been developing continuously. However, actual performance of software cannot keep up with the speed of development in hardware technologies, because hardware architectures become more and more complicated and hardware scales become larger. So, software technique to utilize high-performance computing systems more efficiently plays more important role in realizing high-performance computing for computational science. In this paper, the effort to enhance software performance on large and complex high-performance computing systems such as performance optimization and parallelization will be presented. Our effort to serve high-performance computational kernels such as high-performance sparse solvers and the achievements through this effort also will be introduced.

• Journal of Information Processing Systems
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• 제9권3호
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• pp.499-510
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• 2013

Hardware-Software co-simulation of a multiple image encryption technique shall be described in this paper. Our proposed multiple image encryption technique is based on the Latin Square Image Cipher (LSIC). First, a carrier image that is based on the Latin Square is generated by using 256-bits of length key. The XOR operation is applied between an input image and the Latin Square Image to generate an encrypted image. Then, the XOR operation is applied between the encrypted image and the second input image to encrypt the second image. This process is continues until the nth input image is encrypted. We achieved hardware co-simulation of the proposed multiple image encryption technique by using the Xilinx System Generator (XSG). This encryption technique is modeled using Simulink and XSG Block set and synthesized onto Virtex 2 pro FPGA device. We validated our proposed technique by using the hardware software co-simulation method.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.201-202
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• 2006

In this paper, we achieved software and hardware implementation of SHA-1 hash function for sensor network. We implemented the software to be compatible with TinySec. In hardware design, we optimized operation logics for small area of hardware and minimized data transitions of register memory for low power design. Designed the software and hardware is verified on commercial sensor motes and our secure motes respectively.