• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.1
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• pp.63-70
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• 2011

In this paper, we are implemented the kasumi cipher algorithm by hardware. In this work, kasumi was designed technology-independently for application such as ASIC or core-based design. The hardware is implemented to be able to calculate both confidentiality and integrity algorithm, and a pipelined KASUMI hardware is used for a core operator to achieve high operation frequency. The proposed block cipher was mapped into EPXA10F1020C1 from Altera and used 22% of Logic Element (LE) and 10% of memory element. The result from implementing in hardware (FPGA) could operate stably in 36.35MHz. Accordingly, the implemented hardware are expected to be effectively used as a good solution for the end-to-end security which is considered as one of the important problems.

• Journal of Information Processing Systems
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• v.15 no.6
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• pp.1406-1421
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• 2019

The Internet-of-Things (IoT) has been deployed in almost every facet of our day to day activities. This is made possible because sensing and data collection devices have been given computing and communication capabilities. The devices implement System-on-Chips (SoCs) that incorporate a lot of functionalities, yet they are severely constrained in terms of memory capacitance, hardware area, and power consumption. With the increase in the functionalities of sensing devices, there is a need for low-cost synthesizable processors to handle control, interfacing, and error processing. The first step in selecting a synthesizable processor core for low-cost devices is to examine the hardware resource utilization to make sure that it fulfills the requirements of the device. This paper gives an analysis of the hardware resource usage of ten synthesizable processors that implement the Reduced Instruction Set Computer Five (RISC-V) Instruction Set Architecture (ISA). All the ten processors are synthesized using Vivado v2018.02. The maximum frequency, area, and power reports are extracted and a comparison is made to determine which processor is ideal for low-cost hardware devices.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.05a
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• pp.466-468
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• 2002

This paper proposes a new type of evolvable hardware for implementing the clone of Moore State machine. The proposed Evolvable Hardware is employed efficient pipeline parallelization, handshaking mechanism and fitness function in FPGA Genetic Algorithm(GA) has known as a method of solving NP problem in various applications. Since a major drawback of the GA is that it needs a long computation time, the hardware implementation of Genetic Algorithm is focused on in recent studies. Conventional hardware GA uses the fired length of chromosome but the proposed Evolvable Hardware uses the variable length of chromosome by the efficient 16 bit Pipeline Unit. Experimental results show that the proposed evolvable hardware is applicable to the implementation of the clone for Moore State machine

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.7
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• pp.1553-1557
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• 2004

A real-time processing system for embedded hardware genetic algorithm is suggested. In order to operate basic module of genetic algorithm in parallel, such as selection, crossover, mutation and evaluation, dual processors based architecture is implemented. The system consists of two Xscale processors and two FPGA with evolvable hardware, which enables to process genetic algorithm efficiently by distributing the computational load of hardware genetic algorithm to each processors equally. The hardware genetic algorithm runs on Linux OS and the resulted chromosome is executed on evolvable hardware in FPGA. Furthermore, the suggested architecture can be extended easily for a couple of connected processors in serial, making it accelerate to compute a real-time hardware genetic algorithm. To investigate the effect of proposed approach, performance comparisons is experimented for an typical computation of genetic algorithm.

• ETRI Journal
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• v.33 no.4
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• pp.611-620
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• 2011

Since card-type one-time password (OTP) generators became available, power and area consumption has been one of the main issues of hardware OTPs. Because relatively smaller batteries and smaller chip areas are available for this type of OTP compared to existing token-type OTPs, it is necessary to implement power-efficient and compact dedicated OTP hardware modules. In this paper, we design and implement a low-power small-area hardware OTP generator based on the Advanced Encryption Standard (AES). First, we implement a prototype AES hardware module using a 350 nm process to verify the effectiveness of our optimization techniques for the SubBytes transform and data storage. Next, we apply the optimized AES to a real-world OTP hardware module which is implemented using a 180 nm process. Our experimental results show the power consumption of our OTP module using the new AES implementation is only 49.4% and 15.0% of those of an HOTP and software-based OTP, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.2
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• pp.157-169
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• 2013

Scale Invariant Feature Transform (SIFT) generates image features widely used to match objects in different images. Previous work on hardware-based SIFT implementation requires excessive internal memory and hardware logic [1]. In this paper, a new hardware organization is proposed to implement SIFT with less memory and hardware cost than the previous work. To this end, a parallel Gaussian filter bank is adopted to eliminate the buffers that store intermediate results because parallel operations allow all intermediate results available at the same time. Furthermore, the processing order is changed from the raster-scan order to the block-by-block order so that the line buffer size storing the source image is also reduced. These techniques trade the reduction of memory size with a slight increase of the execution time and external memory bandwidth. As a result, the memory size is reduced by 94.4%. The proposed hardware for SIFT implementation includes the Descriptor generation block, which is omitted in the previous work [1]. The addition of the hardwired descriptor generation improves the computation speed by about 30 times when compared with the previous work.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.5
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• pp.718-723
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• 2002

This paper proposes a new type of evolvable hardware for implementing the clone of Moore State machine. The proposed Evolvable Hardware is employed efficient pipeline parallelization, handshaking mechanism and fitness function in FPGA. Genetic Algorithm(GA) has known as a method of solving NP problem in various applications. Since a major drawback of the GA is that it needs a long computation time, the hardware implementation of Genetic Algorithm is focused on in recent studies. Conventional hardware GA uses the fixed length of chromosome but the proposed Evolvable Hardware uses the variable length of chromosome by the efficient 16 bit Pipeline Unit. Experimental results show that the proposed evolvable hardware is applicable to the implementation of the clone for Moore State machine.

• Journal of the Korean Society of Safety
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• v.34 no.1
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• pp.21-26
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• 2019

This paper is purposed to develop hardware for controlling abnormal temperature that can occur environment and component itself in PCS. In order to be purpose, the hardware which is four part(sensing, PLC, monitoring and output) keep detecting temperature for critical components of PCS and can control the abnormal temperature. Apply to the hardware, it is selected to PV power generation facilities of 20 kW in Cheong-ju city and measured the data for one year in 2017. Through the temperature data, it is found critical components of four(discharge resistance, DC capacitor, IGBT, DSP board) and entered the setting value for operating the fan. The setting values for operating the fan are up to $130^{\circ}C$ in discharge resistance, $60^{\circ}C$ in DC capacitor, $55^{\circ}C$ in IGBT and DSP board. The hardware is installed at the same PCS(20 kW in Cheong-ju city) in 2018 and the power generation output is analyzed for the five days with the highest atmospheric temperature(Clear day) in July and August in 2017 and 2018 years. Therefore, the power generation output of the PV system with hardware increased up to 4 kWh.

• Journal of KIISE:Software and Applications
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• v.37 no.4
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• pp.323-339
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• 2010

The complexity of embedded systems and the effort to develop them has been rising in proportion with their importance. Also, the heterogeneity of the hardware and software parts in embedded systems makes it more challenging to develop. Errors caused by hardware/software interfaces, especially, account for up to 13 percent of failures with an increasing trend. Therefore, verifying the interface between hardware and software in embedded system is one of the most important research areas. However, current approaches such as co-simulation method and model checking have explicit limitations. In this paper, we propose the synthesizable interface co-verification framework for hardware/software co-design. Firstly, we introduce the separate interface specifications for the heterogeneous components to describe hardware design and software design. Our specifications are expressive enough to describe both. We also provide the transformation rules from the software specification to the hardware specification so that the whole system can be described from the software view. Secondly, we address the solution of verifying the interface of the software and hardware design by adopting and extending existing verification-techniques and extending them. In hardware interface verification, we exploit the model checking technique and provide more efficient verification by closing the hardware design from the assumption of the software behavior which is ensured by software verification step. Lastly, we generate the interface codes such as device APIs, device driver, and device controller from the specification so that verified hardware and software codes can be synthesized without extra efforts.

• 제어로봇시스템학회:학술대회논문집
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• 1997.10a
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• pp.1334-1337
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• 1997

A spacecraft attitude control ground hardware simulator development is discussed in the paper. The simulator is called KT/KARI HILSSAT(Hardware-In-the Loop Simulator Single Axis Testbed), and the main structure consists of a single axis bearing and a satellite main body model on the bearing. The single axis tabel as ans experimental hardware simulator that evaluates performance and applicability of a satellite before evolving and/or confirming a mew or and old control logic used in the KOREASAT is developed. Attitude control of spaceraft by using reaction wheel is performed.