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The clone of Moore machine using hardware genetic algorithm  

서기성 (서경대학교 전자공학과)
박세현 (안동대학교 전자정보산업학부)
권혁수 (안동대학교 전자정보산업학부)
이정환 (안동대학교 전자정보산업학부)
노석호 (안동대학교 전자정보산업학부)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.6, no.5, 2002 , pp. 718-723 More about this Journal
Abstract
This paper proposes a new type of evolvable hardware for implementing the clone of Moore State machine. The proposed Evolvable Hardware is employed efficient pipeline parallelization, handshaking mechanism and fitness function in FPGA. Genetic Algorithm(GA) has known as a method of solving NP problem in various applications. Since a major drawback of the GA is that it needs a long computation time, the hardware implementation of Genetic Algorithm is focused on in recent studies. Conventional hardware GA uses the fixed length of chromosome but the proposed Evolvable Hardware uses the variable length of chromosome by the efficient 16 bit Pipeline Unit. Experimental results show that the proposed evolvable hardware is applicable to the implementation of the clone for Moore State machine.
Keywords
FPGA;
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