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Real-time processing system for embedded hardware genetic algorithm  

Park Se-hyun (안동대학교)
Seo Ki-sung (안동대학교)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.8, no.7, 2004 , pp. 1553-1557 More about this Journal
Abstract
A real-time processing system for embedded hardware genetic algorithm is suggested. In order to operate basic module of genetic algorithm in parallel, such as selection, crossover, mutation and evaluation, dual processors based architecture is implemented. The system consists of two Xscale processors and two FPGA with evolvable hardware, which enables to process genetic algorithm efficiently by distributing the computational load of hardware genetic algorithm to each processors equally. The hardware genetic algorithm runs on Linux OS and the resulted chromosome is executed on evolvable hardware in FPGA. Furthermore, the suggested architecture can be extended easily for a couple of connected processors in serial, making it accelerate to compute a real-time hardware genetic algorithm. To investigate the effect of proposed approach, performance comparisons is experimented for an typical computation of genetic algorithm.
Keywords
FPGA;
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