• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 학술대회지
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• pp.509-513
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• 2004

An area of research called evolvable hardware (EHW) has recently emerged which combines aspects of evolutionary computation with hardware design and synthesis. The features that can be used to identify and classify evolvable hardware are the evolutionary algorithm, the implementation and the genotype representation. This paper gives an introduction to the field. It continues by including classifying the EHW and the applications of the area.

• 전자공학회논문지B
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• 제31B권7호
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• pp.129-140
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• 1994

In this paper we investigate the hardware implementation of block matching algorithms (BMAs) for moving sequences. Using systolic arrays we propose a hardware architecture of a two-stage BMA using integral projections which reduces greatly computational complexity with its performance comparable to that of the full search (FS). Proposed hardware architecture is faster than hardware architecture of the FS by 2~15 times. For realization of the FS and two stage BMA modeling and simulation results using SPW and VHDL are also shown.

• 한국수학교육학회지시리즈A:수학교육
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• 제47권4호
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• pp.505-517
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• 2008

This paper studies on the necessity of mathematics/statistics in software and hardware fields. First, this research analyzes the contents of mathematics/statistics among subjects in software and hardware fields. Secondly, this research explores the relationship and connectivity between mathematics/statistics and major tracks of software and hardware fields. This connectivity between mathematics/statistics and majors in software and hardware fields would certainly contribute to creating pragmatic and professional knowledge.

• 한국정보과학회논문지:소프트웨어및응용
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• 제31권10호
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• pp.1364-1373
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• 2004

진화 하드웨어(Evolvable Hardware)는 환경에 적응하여 스스로 구성을 변경할 수 있는 하드웨어로 생산성 향상 및 독창적 회로설계를 위해 최근 널리 연구되고 있다 하지만, 하드웨어의 복잡도가 증가할수록 진화를 위해 탐색해야 하는 해공간의 크기가 기하급수적으로 증가하기 때문에 아직까지 복잡한 하드웨어에 대해서는 좋은 활용방안을 찾지 못하고 있다. 이 논문에서는 좀더 효율적인 설계를 위하여 복잡한 하드웨어를 모듈별로 나누어 진화시키는 방법을 제시한다. 몇 가지 회로를 기존 회로 진화 설계방식과 제시하는 모듈진화 방식으로 실험하여 비교한 결과 약 50배에서 1,000배까지의 세대절약 효과를 얻을 수 있었으며, 좀더 최적화된 하드웨어를 얻을 수 있었다.

• 대한안전경영과학회지
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• 제15권2호
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• pp.63-69
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• 2013

The purposes of this study are to survey stereotypes of control-display relationships for seven principal controls in passenger cars using the paper-pencil and hardware tests, and to examine stereotype strength of the paper-pencil test through comparing the stereotypes for the controls derived by the two methods. Ninety two and 60 college-aged students participated in the paper-pencil test and the real car simulation of the hardware test, respectively. There are dominant motion-directions for all controls in the paper-pencil test, while in the hardware test, there are dominant motion-directions for six controls including head light, high beam, door window, ignition key, door key and door lock controls. The stereotypes of motion-directions for six controls obtained by the paper-pencil test were the same as or similar to those by the hardware test. It was inferred from this that the congruence of the stereotypes by the two methods might be attributed to two simple motion-direction principles of 'clockwise for increase' and 'upward for increase.' Although it is known that the hardware test would be best for obtaining accurate stereotypes between controls and displays, this study implies that if the paper-pencil test is well designed, the paper-pencil test can produce the same results as the hardware test at low cost and without consuming time.

• 전기전자학회논문지
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• 제25권1호
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• pp.10-14
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• 2021

본 논문에서는 기존 CIE1931 색 좌표계를 이용한 색상 보정 연산의 복잡성을 개선한 하드웨어를 제안한다. 기존 알고리즘은 연산 과정에서 큰 비트 수를 계산하기 위해 사용되는 4-Split Multiply 연산으로 인해 하드웨어가 커지는 단점이 있다. 제안하는 알고리즘은 기존 알고리즘의 정의된 R2X, X2R 연산을 미리 계산하여 하나의 행렬로 만들어 영상에 적용함으로써 연산량 감소와 하드웨어 크기 감소가 가능하다. Verilog로 설계된 하드웨어의 Xilinx 합성 결과를 비교함으로써 하드웨어 자원 감소와 4K 환경 실시간 처리를 위한 성능을 확인할 수 있다. 또한, FPGA 보드에서의 실행 결과를 제시함으로써 하드웨어 탑재 동작을 검증하였다.

• ETRI Journal
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• 제45권2호
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• pp.346-357
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• 2023

Hardware security primitives, also known as physical unclonable functions (PUFs), perform innovative roles to extract the randomness unique to specific hardware. This paper proposes a novel hardware security primitive using a commercial off-the-shelf flash memory chip that is an intrinsic part of most commercial Internet of Things (IoT) devices. First, we define a hardware security source model to describe a hardware-based fixed random bit generator for use in security applications, such as cryptographic key generation. Then, we propose a hardware security primitive with flash memory by exploiting the variability of tunneling electrons in the floating gate. In accordance with the requirements for robustness against the environment, timing variations, and random errors, we developed an adaptive extraction algorithm for the flash PUF. Experimental results show that the proposed flash PUF successfully generates a fixed random response, where the uniqueness is 49.1%, steadiness is 3.8%, uniformity is 50.2%, and min-entropy per bit is 0.87. Thus, our approach can be applied to security applications with reliability and satisfy high-entropy requirements, such as cryptographic key generation for IoT devices.

• 한국정보전자통신기술학회논문지
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• 제10권2호
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• pp.192-197
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• 2017

본 논문은 저전력 영상 특징 추출 하드웨어 설계를 위한 공통 부분식 제거 기법 기반 이미지 필터 하드웨어 최적화 기법을 제안한다. 저전력 및 고성능 물체인식 하드웨어는 공장 자동화를 위한 산업용 로봇에 필수 모듈로 채택되고 있다. 따라서 물체인식 하드웨어의 영상 특징 추출 알고리즘에 다양하게 적용되는 Gaussian gradient 필터 하드웨어의 저면적 설계가 필수적이다. Gaussian gradient 필터의 하드웨어 복잡도를 줄이기 위해 필터에 사용되는 계수의 Symmetric한 특징과 Transposed form FIR 필터 하드웨어 구조를 이용했다. 제안된 이미지 필터의 하드웨어 구조는 알고리즘에 적용된 계수의 변형 없이 구현되었기 때문에 윤곽선 검출 알고리즘에 적용했을 때 검출 데이터의 열화 없이 구현될 수 있다. 제안된 이미지 필터 하드웨어 구조는 기존 구조와 비교했을 때 곱셈기의 수를 50% 절감할 수 있음을 확인했다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 학술대회 논문집 정보 및 제어부문
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• pp.309-311
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• 2005

In general, for specific applications, customized hardware showed better performance than general processor in terms of processing time and power consumption. However, customized hardware systems have lacks of flexibility in nature and it leads the difficulties for debugging and architecture level revision for performance enhancement. To solve this problem, reconfigurable hardware is developed. Proposed reconfigurable hardware architecture for FIR filter system can easily change the architecture of filter blocks including filter tap size and their signal path. Proposed FIR filter architecture was implemented on FPGA using several MUXs and registers and it showed the reconfigurablility and reusability in several examples.

• 한국컴퓨터정보학회논문지
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• 제22권8호
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• pp.47-53
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• 2017

In this paper, we present open hardware platforms for Internet of Things (IoTs) emphasizing their strengths and weaknesses. We introduce six representative platforms, Raspberry PI, Arduino, Garileo, Edison, Beagle board and Artik. We define important performance issues for open hardware platforms for IoTs and analyze recent platforms according to the performance issues. We present recent research project using open hardware platforms introduced in this paper. We believe that this paper provide wise view and necessary information for open hardware platforms for Internet of Things (IoT).