• 전력전자학회:학술대회논문집
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• 전력전자학회 1998년도 Proceedings ICPE 98 1998 International Conference on Power Electronics
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• pp.914-919
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• 1998

A Capacitor Commutated Converter (CCC) has less difficulty of commutation failure in comparison to the conventional line commutated converter. This paper proposes the Ar1R control of the CCC in the inverter operation, which deserves as the Ar1R of the conventional converter. The CCC can be operated in high power factor area by using the proposing Ar1R control. The voltage stability at an AC bus connected the CCC inverter is investigated and estimated its ability of preventing the AC voltage collapse. To estimate the voltage stability, this paper developed the simplified converter mathematical model and led the VSF index. The results shows that the AC voltage stability is guaranteed and enables the interconnection to an weak AC system, when compensation factor of the compensation capacitor is higher than 200%.

• 전력전자학회논문지
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• 제21권1호
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• pp.49-57
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• 2016

A modular multilevel converter is widely adapted for a high-voltage direct current power transmission system. This study proposes a design methodology for a novel digital control that mitigates the negative effects caused by time delay, including communication transport delay for a modular multilevel converter. The modeling and negative effect of time delay are analyzed theoretically in a frequency domain, and its compensation methodology based on an inverse model is described fully with practical considerations. The proposed methodology is verified through several simulation results using a modular 21-level converter system.

• Journal of Electrical Engineering and Technology
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• 제9권5호
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• pp.1746-1752
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• 2014

This paper presents an application of proportional-resonant (PR) current controllers in modular multilevel converter-high voltage direct current (MMC-HVDC) system under unbalanced voltage conditions. The ac currents are transformed and controlled in the stationary reference frame (${\alpha}{\beta}$-frame). Thus, the complex analysis of the positive and negative sequence components in the synchronous rotating reference frame (dq-frame) is not necessary. With this control method, the ac currents are kept balanced and the dc-link voltage is constant under the unbalanced voltage fault conditions. The simulation results based on a detailed PSCAD/EMTDC model confirm the effectiveness of the proposed control method.

• Journal of Power Electronics
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• 제19권6호
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• pp.1486-1495
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• 2019

Dealing with the DC link fault poses a technical problem for an HVDC based on a modular multilevel converter. The fault suppressing mechanisms of several sub-module topologies with DC fault current blocking capacity are examined in this paper. An improved half-bridge sub-module topology with double direction control switch is also designed to address the additional power consumption problem, and a sub-module topology called hybrid double direction blocking sub module (HDDBSM) is proposed. The DC fault suppression characteristics and sub-module capacitor voltage balance problem is also analyzed, and a self-startup method is designed according to the number of capacitors. The simulation model in PSCAD/EMTDC is built to verify the self-startup process and the DC link fault suppression features.

• 한국산업융합학회 논문집
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• 제24권4_1호
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• pp.411-419
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• 2021

In this study, IGBT_Total_Loss and DIODE_Total_Loss were used to analyze the slope of the junction temperature for each section for temperature and duty variables in order to simply calculate the junction temperature of the power semiconductor (IGBT). As a result of the calculation, IGBT_Max_Junction_Temp and DIODE_Max_Junction_Temp form a proportional relationship with temperature for each duty. This simulation data shows that the power loss of a power semiconductor is calculated in a complex manner according to the current dependence index, voltage dependence index, and temperature coefficient. By applying the slope for each condition and section, the junction temperature of the power semiconductor can be calculated simply.

• Journal of Power Electronics
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• 제17권2호
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• pp.346-357
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• 2017

The Modular Multilevel Converter (MMC) is particularly attractive for medium and high power applications such as High-Voltage Direct Current (HVDC) systems. In order to reach a high voltage, the number of cascaded submodules (SMs) is generally very large. Thus, in the applications with hundreds or even thousands of SMs such as MMC-HVDCs, the sorting algorithm of the conventional voltage balancing strategy is extremely slow. This complicates the controller design and increases the hardware cost tremendously. This paper presents a Two-Way Merge Sort (TWMS) strategy based on the prediction of the capacitor voltages under ideal conditions. It also proposes an innovative Insertion Sort Correction for the TWMS (ISC-TWMS) to solve issues in practical engineering under non-ideal conditions. The proposed sorting methods are combined with the features of the MMC-HVDC control strategy, which significantly accelerates the sorting process and reduces the implementation efforts. In comparison with the commonly used quicksort algorithm, it saves at least two-thirds of the sorting execution time in one arm with 100 SMs, and saves more with a higher number of SMs. A 501-level MMC-HVDC simulation model in PSCAD/EMTDC has been built to verify the validity of the proposed strategies. The fast speed and high efficiency of the algorithms are demonstrated by experiments with a DSP controller (TMS320F28335).

• Journal of Electrical Engineering and Technology
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• 제10권3호
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• pp.935-943
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• 2015

Permanent magnetic actuators (P.M.A.s) are widely used to drive medium-voltage-class vacuum circuit breakers (V.C.B.s). In this paper, a method for design optimization of a P.M.A. for V.C.B.s is discussed. An optimal design process employing the response surface method (R.S.M.) is proposed. In order to calculate electromagnetic and mechanical dynamic characteristics, an initial P.M.A. model is subjected to numerical analysis using finite element analysis (F.E.A.), which is validated by comparing the calculated dynamic characteristics of the initial P.M.A. model with no-load test results. Using tables of mixed orthogonal arrays and the R.S.M., the initial P.M.A. model is optimized to minimize the weight of the permanent magnet (P.M.) and to improve the dynamic characteristics. Finally, the dynamic characteristics of the optimally designed P.M.A. are compared to those of the initially designed P.M.A.

• Journal of Power Electronics
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• 제18권6호
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• pp.1920-1929
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• 2018

In order to provide a source for nine phases suitable for 18-pulse ac to dc power, this paper proposes a new structure for a step-up asymmetrical delta-connected transformer for converting three-phase ac power to nine-phase ac power. The design allows for symmetry between the nine output voltages to improve the power quality of the supply current and to minimize the THD. The results show that this new structure proves the equality between the output voltages with $40^{\circ}-{\alpha}$ and $40^{\circ}+{\alpha}$ phase shifting and produces symmetrical output currents. This result in the elimination of harmonics in the network current and provides a simulated THD that is equal to 5.12 %. An experimental prototype of the step-up asymmetrical delta-autotransformer is developed in the laboratory and the obtained results give a network current with a THD that is equal to 5.35%. Furthermore, a finite element analysis with a 3D magnetic field model is made based on the dimensions of the 4kVA, 400 V laboratory prototype three-phase with three-limb delta-autotransformer with a six-stacked-core in each limb. The magnetic distribution flux, field intensity and magnetic energy are carried out under open-circuit operation or load-loss.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2011년도 제42회 하계학술대회
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• pp.822-823
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• 2011

The authors analyzed harmonic current based loss of a high temperature superconducting (HTS) DC model cable. The loss in HTS DC cable is generated due to the variation of magnetic field caused by harmonic current in a HVDC transmission system. The authors designed and fabricated two meters of HTS DC model cable for verification of real loss characteristic. In this paper, the loss characteristics caused by harmonic current in the HTS DC model cable are analyzed using commercial finite element method software package. The loss of the HTS DC cable is much less than the loss of the HTS AC cable but the loss should be considered to decide a proper capacity of cooling system.

• 한국초전도ㆍ저온공학회논문지
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• 제5권2호
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• pp.1-7
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• 2003

Nowadays, one of the serious problems in KEPCO(Korea Electric Power Co-Operation) system is the more higher fault current than the SCC(Short Circuit Capacity) of circuit breaker. There are many alternatives to reduce the increased fault current such as isolations of bus ties, enhancement of SCC of circuit breaker, applications of HVDC-BTB(High Voltage Direct Current-Back to Back) and FCL(fault current limiter). But, these alternatives have some drawbacks in viewpoints of system stability and cost. As the superconductivity technology has been developed, the HTS-FCL(High Temperature Superconductor -Fault Current Limiter) can be one of the attractive alternatives to solve the fault current problem. Under this background, this paper presents the EMTDC(Electro-Magnetic Transient Direct Current) model for resistance type HTS-FCL considering the nonlinear characteristic of final resistance value when quenching phenomena occur.