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http://dx.doi.org/10.6113/TKPE.2016.21.1.49

A Design Methodology of Digital Controller Considering Time Delay Effect for a Modular Multilevel Converter VSC HVDC System  

Song, Ji-Wan (Dept. of Electrical Eng., EECS Lab., Hanyang University)
Ku, Nam-Joon (Dept. of Electrical Eng., EECS Lab., Hanyang University)
Kim, Rae-Young (Dept. of Electrical and Biomedical Eng., Hanyang University)
Publication Information
The Transactions of the Korean Institute of Power Electronics / v.21, no.1, 2016 , pp. 49-57 More about this Journal
Abstract
A modular multilevel converter is widely adapted for a high-voltage direct current power transmission system. This study proposes a design methodology for a novel digital control that mitigates the negative effects caused by time delay, including communication transport delay for a modular multilevel converter. The modeling and negative effect of time delay are analyzed theoretically in a frequency domain, and its compensation methodology based on an inverse model is described fully with practical considerations. The proposed methodology is verified through several simulation results using a modular 21-level converter system.
Keywords
Time delay effect; Modular multilevel converter; Digital control; High voltage direct current;
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