• Title/Summary/Keyword: HEVC encoder

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Statistical Characteristics and Complexity Analysis of HEVC Encoder Software (HEVC 부호화기 소프트웨어의 통계적 특성 및 복잡도 분석)

  • Ahn, Yongjo;Hwang, Taejin;Yoo, Sungeun;Han, Woo-Jin;Sim, Donggyu
    • Journal of Broadcast Engineering
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    • v.17 no.6
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    • pp.1091-1105
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    • 2012
  • In this paper, we analyzed statistical characteristics and complexity of HEVC encoder as a leading research of acceleration, optimization and parallelization. Computational complexity of the HEVC encoder is approximately twice the compression performance compared to H.264/AVC. But, the increase of encoder complexity remains a problem to be solved in the future. Before performing the research on acceleration, optimization and parallelization to reduce high complexity of HEVC encoder, we measure the complexity each module for HEVC encoder using it's reference software HM 7.1. We also measured the predicted complexity of fast HEVC encoder software, used in real applications, using HM 7.1 applying fast encoding method. The complexity is measured in terms of the operating cycle of the encoder software under the common test sequences and conditions in the Windows PC environment. In addition, we analyze statistical characteristics of HEVC encoder software according to encoding structures and limitation using coded bitstreams.

Optimized Implementation of Interpolation Filters for HEVC Encoder

  • Taejin, Hwang;Ahn, Yongjo;Ryu, Jiwoo;Sim, Donggyu
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.10
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    • pp.199-203
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    • 2013
  • In this paper, a fast algorithm of discrete cosine transform-based interpolation filter (DCT-IF) for HEVC (high efficiency video coding) encoder is proposed. DCT-IF filter accounts for around 30% of encoder complexity, according to the computational complexity analysis with the HEVC reference software. In this work, the proposed DCT-IF is optimized by applying frame-level interpolation, SIMD optimization, and task-level parallelization via OpenMP on a developed C-based HEVC encoder. Performance analysis is conducted by measuring speed-up factor of the proposed optimization technique on the developed encoder. The results show that speed-up factors by frame-level interpolation, SIMD, and OpenMP are approximately 38-46, 3.6-4.4, and 3.0-3.7, respectively. In the end, we achieved the speed-up factor of 498.4 with the proposed fast algorithm.

Study of Parallelization Methods for Software based Real-time HEVC Encoder Implementation (소프트웨어 기반 실시간 HEVC 인코더 구현을 위한 병렬화 기법에 관한 연구)

  • Ahn, Yong-Jo;Hwang, Tae-Jin;Lee, Dongkyu;Kim, Sangmin;Oh, Seoung-Jun;Sim, Dong-Gyu
    • Journal of Broadcast Engineering
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    • v.18 no.6
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    • pp.835-849
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    • 2013
  • Joint Collaborative Team on Video Coding (JCT-VC), which have founded ISO/IEC MPEG and ITU-T VCEG, has standardized High Efficiency Video Coding (HEVC). Standardization of HEVC has started with purpose of twice or more coding performance compared to H.264/AVC. However, flexible and hierarchical coding block and recursive coding structure are problems to overcome of HEVC standard. Many fast encoding algorithms for reducing computational complexity of HEVC encoder have been proposed. However, it is hard to implement a real-time HEVC encoder only with those fast encoding algorithms. In this paper, for implementation of software-based real-time HEVC encoder, data-level parallelism using SIMD instructions and CPU/GPU multi-threading methods are proposed. And we also proposed appropriate operations and functional modules to apply the proposed methods on HM 10.0 software. Evaluation of the proposed methods implemented on HM 10.0 software showed 20-30fps for $832{\times}480$ sequences and 5-10fps for $1920{\times}1080$ sequences, respectively.

Fast Prediction Unit Decision Using Quantized Transform Coefficient (양자화된 트랜스폼 계수를 이용한 고속 Prediction Unit 결정방법)

  • Gweon, Ryeong-Hee;Lee, Yung-Lyul
    • Journal of Broadcast Engineering
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    • v.17 no.5
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    • pp.725-733
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    • 2012
  • MPEG and VCEG have constituted a collaboration team called JCT-VC(Joint Collaborative Team on Video Coding) and have been developing the HEVC(High Efficiency Video Coding) standard. The next generation video coding standard HEVC shows higher compression rate compared with the H.264/AVC standard, but the encoder computational complexity of the HEVC encoder is significantly high. In order to reduce this computational complexity in the HEVC encoder, a fast prediction unit decision is proposed. The proposed fast prediction unit decision method reduces the encoder complexity by skipping the remaining prediction units if the current prediction unit does not have any non-zero quantized transform coefficient. The proposed method reduces the encoder computational complexity by 50.3% comparing with HM6.0 but it maintains the same level of coding efficiency.

Early Decision of Inter-prediction Modes in HEVC Encoder (HEVC 부호화기에서의 화면 간 예측모드 고속 결정)

  • Han, Woo-Jin;Ahn, Joon-Hyung;Lee, Jong-Ho
    • Journal of Broadcast Engineering
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    • v.20 no.1
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    • pp.171-182
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    • 2015
  • HEVC can increase the coding efficiency significantly compared with H.264/AVC however it requires much larger computational complexities in both encoder and decoder. In this paper, the decision process of inter-prediction modes in the HEVC reference software has been studied and a fast algorithm to reduce the computational complexity of encoder and decoder is introduced. The proposed scheme introduces a early decision criteria using the outputs of uni-directional predictions to skip the bi-directional prediction estimation. From the experimental results, it was proven that the proposed method can reduce the encoding complexity by 12.0%, 14.6% and 17.2% with 0.6%, 1.0% and 1.5% of coding efficiency penalty, respectively. In addition, the ratio of bi-directional prediction mode was reduced by 6.3%, 11.8% and 16.6% at the same level of coding efficiency penalty, respectively, which should lead to the decoder complexity reduction. Finally, the effects of the proposed scheme are maintained regardless of the use of the early skip decision algorithm which is implemented in the HEVC reference software.

Efficient QP-per-frame Assignment Method for Low-delay HEVC Encoder (저지연 HEVC 부호화기를 위한 효율적인 프레임별 양자화 파라미터 할당 방법)

  • Park, Sang-hyo;Jang, Euee S.
    • Journal of Broadcast Engineering
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    • v.21 no.3
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    • pp.349-356
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    • 2016
  • In this paper, we propose an efficient assignment method that assigns quantization parameter (QP) in accordance with group of picture (GOP) structure given in HEVC encoder. Each video frames can have difference QP values based on given GOP configuration for HEVC encoding. Particularly, for important frames we can assign low QP values, and vice versa. However, there has not been thorough investigation on efficient QP assignment method by far. Even in HEVC reference software encoder, only monotonic QP assignment method is employed. Thus, the proposed method assign adaptive QP values to each GOP so that temporal dynamic activity between GOPs can be exploited. Through the experiment, the proposed method showed a 7.3% gain of compression performance in terms of BD-rate compared to HEVC test model (HM) in low-delay configuration, and outperformed the existing QP assignment study on average.

A Study on the Hardware Design of High-Throughput HEVC CABAC Binary Arithmetic Encoder (높은 처리량을 갖는 HEVC CABAC 이진 산술 부호화기의 하드웨어 설계에 관한 연구)

  • Jo, Hyun-gu;Ryoo, Kwang-ki
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2016.10a
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    • pp.401-404
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    • 2016
  • This paper proposes entropy coding method of HEVC CABAC Encoder for efficient hardware architecture. The Binary Arithmetic Encoder requires data dependency at each step, which is difficult to be operated in a fast. Proposed Binary Arithmetic Encoder is designed 4 stage pipeline to quickly process the input value bin. According to bin approach, either MPS or LPS is selected and the binary arithmetic encoding is performed. Critical path caused by repeated operation is reduced by using the LUT and designed as a shift operation which decreases hardware size and not using memory. The proposed Binary Arithmetic Encoder of CABAC is designed using Verilog-HDL and it was implemented in 65nm technology. Its gate count is 3.17k and operating speed is 1.53GHz.

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Hardware Implementation of HEVC CABAC Binary Arithmetic Encoder

  • Pham, Duyen Hai;Moon, Jeonhak;Kim, Doohwan;Lee, Seongsoo
    • Journal of IKEEE
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    • v.18 no.4
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    • pp.630-635
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    • 2014
  • In this paper, hardware architecture of BAE (binary arithmetic encoder) was proposed for HEVC (high efficiency video coding) CABAC (context-based adaptive binary arithmetic coding) encoder. It can encode each bin in a single cycle. It consists of controller, regular encoding engine, bypass encoding engine, and termination engine. The proposed BAE was designed in Verilog HDL, and it was implemented in 180 nm technology. Its operating speed, gate count, and power consumption are 180 MHz, 3,690 gates, and 2.88 mW, respectively.

Integer-Pel Motion Estimation for HEVC on Compute Unified Device Architecture (CUDA)

  • Lee, Dongkyu;Sim, Donggyu;Oh, Seoung-Jun
    • IEIE Transactions on Smart Processing and Computing
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    • v.3 no.6
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    • pp.397-403
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    • 2014
  • A new video compression standard called High Efficiency Video Coding (HEVC) has recently been released onto the market. HEVC provides higher coding performance compared to previous standards, but at the cost of a significant increase in encoding complexity, particularly in motion estimation (ME). At the same time, the computing capabilities of Graphics Processing Units (GPUs) have become more powerful. This paper proposes a parallel integer-pel ME (IME) algorithm for HEVC on GPU using the Compute Unified Device Architecture (CUDA). In the proposed IME, concurrent parallel reduction (CPR) is introduced. CPR performs several parallel reduction (PR) operations concurrently to solve two problems in conventional PR; low thread utilization and high thread synchronization latency. The proposed encoder reduces the portion of IME in the encoder to almost zero with a 2.3% increase in bitrate. In terms of IME, the proposed IME is up to 172.6 times faster than the IME in the HEVC reference model.

Hardware Design of In-loop Filter for High Performance HEVC Encoder (고성능 HEVC 부호기를 위한 루프 내 필터 하드웨어 설계)

  • Park, Seungyong;Im, Junseong;Ryoo, Kwangki
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.20 no.2
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    • pp.335-342
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    • 2016
  • This paper proposes efficient hardware structure of in-loop filter for a high-performance HEVC (High Efficiency Video Coding) encoder. HEVC uses in-loop filter consisting of deblocking filter and SAO (Sample Adaptive Offset) to improve the picture quality in a reconstructed image due to a quantization error. However, in-loop filter causes an increase in complexity due to the additional encoder and decoder operations. A proposed in-loop filter is implemented as a three-stage pipeline to perform the deblocking filtering and SAO operation with a reduced number of cycles. The proposed deblocking filter is also implemented as a six-stage pipeline to improve efficiency and performs a new filtering order for efficient memory architecture. The proposed SAO processes six pixels parallelly at a time to reduce execution cycles. The proposed in-loop filter encoder architecture is designed by Verilog HDL, and implemented by 131K logic gates in TSMC $0.13{\mu}m$ process. At 164MHz, the proposed in-loop filter encoder can support 4K Ultra HD video encoding at 60fps in real time.