• Title/Summary/Keyword: HEVC decoder

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Weighted Prediction considering Global Brightness Variation and Local Brightness Variation in HEVC (전체적 밝기 변화와 지역적 밝기 변화를 고려한 HEVC에서의 가중치 예측)

  • Lim, Sung-won;Moon, Joo-hee
    • Journal of Broadcast Engineering
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    • v.20 no.4
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    • pp.489-496
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    • 2015
  • In this paper, a new weighted prediction scheme is proposed to improve the coding efficiency for video scenes containing brightness variations. Conventional weighted prediction is applied by the reference picture and use only one weighted parameter set. Thus, it is only useful for GBV(Glabal Brightness Variation). In order to solve this problem, the proposed algorithm use three kind of schemes depending on situation. Experimental results show that maximum coding efficiency gain of the proposed method is up to 10.2% in luminance. Average computional time complexity is increased about 163% in encoder and about 101% in decoder.

An Efficient Hardware Design of Intra Predictor for High Performance HEVC Decoder (고성능 HEVC 복호기를 위한 화면내 예측기의 효율적인 하드웨어 설계)

  • Jung, Hongkyun;Kang, Sukmin;Ryoo, Kwangki
    • Proceedings of the Korea Information Processing Society Conference
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    • 2012.11a
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    • pp.668-671
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    • 2012
  • 본 논문에서는 차세대 비디오 압축 표준인 HEVC(High Efficiency Video Coding) 복호기의 연산량과 하드웨어 면적을 감소시키기 위하여 화면내 예측 하드웨어 구조를 제안한다. 제안하는 하드웨어 구조는 공통 수식에 대한 연산을 공유하는 공유 연산기를 사용하여 연산량 및 연산기 개수를 감소시키고, $4{\times}4$ PU와 $64{\times}64$ PU의 필터링 수행 여부에 대한 연산을 수행하지 않고 나머지 PU에 대해서는 LUT를 이용하여 연산을 수행하기 때문에 연산량 및 연산 시간을 감소시킨다. 또한 하나의 공통 연산기만을 사용하여 예측 픽셀을 생성하기 때문에 하드웨어 면적이 감소한다. 제안하는 구조를 TSMC 0.18um 공정을 이용하여 합성한 결과 최대 동작 주파수는 100MHz이고, 게이트 수는 140,697이다. $4{\times}4$ PU를 기준으로 제안하는 구조의 처리 사이클 수는 11 사이클로 기존 구조 대비 54% 감소하였고, 16개 참조 픽셀의 필터링 처리를 기준으로 제안하는 구조의 덧셈 연산기 개수는 37개로 표준 draft 6에 비해 22.9% 감소하였다.

Implementation of SEI Parser and Decoder for Virtual Reality Video Projection Processing (가상 현실 비디오 프로젝션 처리를 위한 SEI 구문 분석기와 디코더 구현)

  • Jeong, JongBeom;Son, Jang-Woo;Jang, Dongmin;Ryu, Eun-Seok
    • Proceedings of the Korean Society of Broadcast Engineers Conference
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    • 2018.06a
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    • pp.1-4
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    • 2018
  • 최근 360 도 가상현실을 지원하기 위한 비디오 시스템은 다양한 프로젝션에 대한 처리를 필요로 한다. 이를 위해 Moving Picture Experts Group (MPEG) 비디오 표준화 기술은 비디오에 대한 추가적인 정보들로 프로젝션을 처리하는 기술을 표준 채택하였다. 즉, 다양한 프로젝션의 비디오에 대응하는 비디오 메타데이터 처리를 H.265/HEVC(High Efficiency Video Coding)에서 제안된 Supplemental Enhancement Information(SEI) 메세지를 사용하여 지원한다. 본 논문은 비디오의 인코딩, 디코딩 시에 비디오 프로젝션 타입에 따라 다르게 처리하는 시스템의 구현 기술을 소개한다. 이를 위해 본 논문은 SEI 메시지 구문 분석기를 구현 시 HEVC Test Model(HM)을 이용하고, 디코더 구현 시 FFmpeg 라이브러리를 이용한다. 최종적으로 구현된 시스템은, 본 기관의 또 다른 구현 물인 실시간 360 비디오 플레이어에 통합되어 실시간 디코딩 및 다양한 프로젝션의 전/후처리를 문제 없이 지원하였다.

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Hardware Design of In-loop Filter for High Performance HEVC Encoder (고성능 HEVC 부호기를 위한 루프 내 필터 하드웨어 설계)

  • Park, Seungyong;Im, Junseong;Ryoo, Kwangki
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.20 no.2
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    • pp.335-342
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    • 2016
  • This paper proposes efficient hardware structure of in-loop filter for a high-performance HEVC (High Efficiency Video Coding) encoder. HEVC uses in-loop filter consisting of deblocking filter and SAO (Sample Adaptive Offset) to improve the picture quality in a reconstructed image due to a quantization error. However, in-loop filter causes an increase in complexity due to the additional encoder and decoder operations. A proposed in-loop filter is implemented as a three-stage pipeline to perform the deblocking filtering and SAO operation with a reduced number of cycles. The proposed deblocking filter is also implemented as a six-stage pipeline to improve efficiency and performs a new filtering order for efficient memory architecture. The proposed SAO processes six pixels parallelly at a time to reduce execution cycles. The proposed in-loop filter encoder architecture is designed by Verilog HDL, and implemented by 131K logic gates in TSMC $0.13{\mu}m$ process. At 164MHz, the proposed in-loop filter encoder can support 4K Ultra HD video encoding at 60fps in real time.

Parallel Deblocking Filter Based on Modified Order of Accessing the Coding Tree Units for HEVC on Multicore Processor

  • Lei, Haiwei;Liu, Wenyi;Wang, Anhong
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.11 no.3
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    • pp.1684-1699
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    • 2017
  • The deblocking filter (DF) reduces blocking artifacts in encoded video sequences, and thereby significantly improves the subjective and objective quality of videos. Statistics show that the DF accounts for 5-18% of the total decoding time in high-efficiency video coding. Therefore, speeding up the DF will improve codec performance, especially for the decoder. In view of the rapid development of multicore technology, we propose a parallel DF scheme based on a modified order of accessing the coding tree units (CTUs) by analyzing the data dependencies between adjacent CTUs. This enables the DF to run in parallel, providing accelerated performance and more flexibility in the degree of parallelism, as well as finer parallel granularity. We additionally solve the problems of variable privatization and thread synchronization in the parallelization of the DF. Finally, the DF module is parallelized based on the HM16.1 reference software using OpenMP technology. The acceleration performance is experimentally tested under various numbers of cores, and the results show that the proposed scheme is very effective at speeding up the DF.

CU-based Merge Candidate List Construction Method for HEVC (HEVC를 위한 CU기반 병합 후보 리스트 구성 방법)

  • Kim, Kyung-Yong;Kim, Sang-Min;Park, Gwang-Hoon;Kim, Hui-Yong;Lim, Sung-Chang;Lee, Jin-Ho
    • Journal of Broadcast Engineering
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    • v.17 no.2
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    • pp.422-425
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    • 2012
  • This paper proposes the CU-based approach for merge candidate list construction for providing reduced complexity and improved parallelism compared to the PU-based one. In the proposed method, a CU can have only one merge candidate list. So, Only one common merge candidate list is used for all PUs in a CU regardless of the PU partition type. The simulation results of proposed method showed that the encoder computational complexity was decreased by 3% to 6% and the decoder computational complexity was negligible change with the penalty of roughly 0.2% - 0.5% coding loss. The proposed method has several advantages: it provides simpler design, reduced complexity, and improved parallelism.

Lossless Image Compression Based on Deep Learning (딥 러닝 기반의 무손실 영상압축 방법)

  • Rhee, Hochang;Cho, Nam Ik
    • Proceedings of the Korean Society of Broadcast Engineers Conference
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    • 2022.06a
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    • pp.67-70
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    • 2022
  • 최근 딥러닝 방법의 발전하면서 영상처리 및 컴퓨터 비전의 다양한 분야에서 딥러닝 기반의 알고리즘들이 그 이전의 방법들에 비하여 큰 성능 향상을 보이고 있다. 손실 영상 압축의 경우 최근 encoder-decoder 형태의 네트웍이 영상 압축에서 사용되는 transform을 대체하고 있고, transform 결과들의 엔트로피 코딩을 위한 추가적인 encoder-decoder 네트웍을 사용하여 HEVC 수준에 버금가는 성능을 내고 있다. 무손실 압축의 경우에도 매 픽셀 예측을 CNN으로 수행하는 경우, 기존의 예측방법들에 비하여 예측성능이 크게 향상되어 JPEG-2000 Lossless, FLIF, JEPG-XL 등의 딥러닝을 사용하지 않는 방법들에 비하여 우수한 성능을 내는 것으로 보고되고 있다. 그러나 모든 픽셀에 대하여 예측값을 CNN을 통하여 계산하는 방법은, 영상의 픽셀 수 만큼 CNN을 수행해야 하므로 HD 크기 영상에 대하여 지금까지 알려진 가장 빠른 방법이 한 시간 이상 소요되는 등 비현실적인 것으로 알려져 있다. 따라서 최근에는 성능은 이보다 떨어지지만 속도를 현실적으로 줄인 방법들이 제안되고 있다. 이러한 방법들은 초기에는 FLIF나 JPEG-XL에 비하여 성능이 떨어져서, GPU를 사용하면서도 기존의 방법보다 좋지 않은 성능을 보인다는 면에서 여전히 비현실적이었다. 최근에는 신호의 특성을 더 잘 활용하는 방법들이 제안되면서 매 픽셀마다 CNN을 수행하는 방법보다는 성능이 떨어지지만, 짧은 시간 내에 FLIF나 JPEG-XL보다는 좋은 성능을 내는 현실적인 방법들이 제안되었다. 본 연구에서는 이러한 최근의 몇 가지 방법들을 살펴보고 이들보다 성능을 더 좋게 할 수 있는 보조적인 방법들과 raw image에 대한 성능을 평가한다.

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Adaptive Intra Prediction Method using Modified Cubic-function and DCT-IF (변형된 3차 함수와 DCT-IF를 이용한 적응적 화면내 예측 방법)

  • Lee, Han-Sik;Lee, Ju-Ock;Moon, Joo-Hee
    • Journal of Broadcast Engineering
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    • v.17 no.5
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    • pp.756-764
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    • 2012
  • In current HEVC, prediction pixels are finally calculated by linear-function interpolation on two reference pixels. It is hard to expect good performance on the case of occurring large difference between two reference pixels. This paper decides more accurate prediction pixel values than current HEVC using linear function. While existing prediction process only uses two reference pixels, proposed method uses DCT-IF. DCT-IF analyses frequency characteristics of more than two reference pixels in frequency domain. And proposed method calculates prediction value adaptively by using linear-function, DCT-IF and cubic-function to decide more accurate interpolation value than to only use linear function. Cubic-function has a steep slope than linear-function. So, using cubic-function is utilized on edge in prediction unit. The complexity of encoder and decoder in HM6.0 has increased 3% and 1%, respectively. BD-rate has decreased 0.4% in luma signal Y, 0.3% in chroma signal U and 0.3% in chroma signal V in average. Through this experiment, proposed adaptive intra prediction method using DCT-IF and cubic-function shows increased performance than HM6.0.

Complexity Reduction of an Adaptive Loop Filter Based on Local Homogeneity

  • Li, Xiang;Ahn, Yongjo;Sim, Donggyu
    • IEIE Transactions on Smart Processing and Computing
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    • v.6 no.2
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    • pp.93-101
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    • 2017
  • This paper proposes an algorithm for adaptive loop filter (ALF) complexity reduction in the decoding process. In the original ALF algorithm, filtering for I frames is performed in the frame unit, and thus, all of the pixels in a frame are filtered if the current frame is an I frame. The proposed algorithm is designed on top of the local gradient calculation. On both the encoder side and the decoder side, homogeneous areas are checked and skipped in the filtering process, and the filter coefficient calculation is only performed in the inhomogeneous areas. The proposed algorithm is implemented in Joint Exploration Model (JEM) version 3.0 future video coding reference software. The proposed algorithm is applied for frame-level filtering and intra configuration. Compared with the JEM 3.0 anchor, the proposed algorithm has 0.31%, 0.76% and 0.73% bit rate loss for luma (Y) and chroma (U and V), respectively, with about an 8% decrease in decoding time.

Fine-scalable SPIHT Hardware Design for Frame Memory Compression in Video Codec

  • Kim, Sunwoong;Jang, Ji Hun;Lee, Hyuk-Jae;Rhee, Chae Eun
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.17 no.3
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    • pp.446-457
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    • 2017
  • In order to reduce the size of frame memory or bus bandwidth, frame memory compression (FMC) recompresses reconstructed or reference frames of video codecs. This paper proposes a novel FMC design based on discrete wavelet transform (DWT) - set partitioning in hierarchical trees (SPIHT), which supports fine-scalable throughput and is area-efficient. In the proposed design, multi-cores with small block sizes are used in parallel instead of a single core with a large block size. In addition, an appropriate pipelining schedule is proposed. Compared to the previous design, the proposed design achieves the processing speed which is closer to the target system speed, and therefore it is more efficient in hardware utilization. In addition, a scheme in which two passes of SPIHT are merged into one pass called merged refinement pass (MRP) is proposed. As the number of shifters decreases and the bit-width of remained shifters is reduced, the size of SPIHT hardware significantly decreases. The proposed FMC encoder and decoder designs achieve the throughputs of 4,448 and 4,000 Mpixels/s, respectively, and their gate counts are 76.5K and 107.8K. When the proposed design is applied to high efficiency video codec (HEVC), it achieves 1.96% lower average BDBR and 0.05 dB higher average BDPSNR than the previous FMC design.