• Journal of Broadcast Engineering
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• v.17 no.1
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• pp.108-121
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• 2012

As Scalable Video Coding (SVC) is a video compression standard extended from H.264/AVC, it is a way to provide scalability in terms of temporal, spatial and quality. Although the compression efficiency of SVC is increased due to the scalability in many aspect, it is essential to reduce the complexity in order to efficiently use because the complexity is relatively increased. To reduce the complexity of SVC in the paper, we propose fast mode decision algorithm to reduce the complexity of encoding process using direction information of B-picture by efficiently performing inter-layer prediction. The proposed algorithm is a fast mode decision algorithm that makes different from detection mode number of forward and backward, bi-direction in the way using best mode of base-layer up-sampled after simply SKIP mode detection using the direction information of best mode of base-layer up-sampled. The experimental results show that the proposed algorithm approach can achieve the maximum computational time saving about 53% with almost no loss of rate distortion (RD) performance in the enhancement layer.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.8 no.3
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• pp.1093-1104
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• 2014

The High Efficiency Video Coding (HEVC) is a new video coding standard that can provide much better compression efficiency than its predecessor H.264/AVC. However, it is computationally more intensive due to the use of flexible quadtree coding unit structure and more choices of prediction modes. In this paper, a fast intraframe coding scheme is proposed for HEVC. Firstly, a fast bottom-up pruning algorithm is designed to skip the mode decision process or reduce the candidate modes at larger block size coding unit. Then, a low complexity rough mode decision process is adopted to choose a small candidate set, followed by early DC and Planar mode decision and mode filtering to further reduce the number of candidate modes. The proposed method is evaluated by the HEVC reference software HM8.2. Averaging over 5 classes of HEVC test sequences, 41.39% encoding time saving is achieved with only 0.77% bitrate increase.

• Journal of information and communication convergence engineering
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• v.8 no.1
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• pp.71-76
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• 2010

Scalable video coding (SVC) has been standardized as an extension of the H.264/AVC standard. SVC allows straightforward adaptation of video streams by providing layered bit streams. In this paper, we propose a SVC video-based multicasting system preserving scalable security which is able to provide a SVC video service while maintaining information security. In order to maintain information security between a server and a client during all transmission time, the proposed system immediately performs a packet filtering process without decoding with respect to encrypted data received in a routing device, thereby reducing an amount of calculations and latency.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1508-1511
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• 2007

This paper introduces a new texture prediction for MVC( Multi-view Video Coding) which is currently being developed as an extension of the ITU-T Recommendation H.264 | ISO/IEC International Standard ISO/IEC 14496-10 AVC (Advanced Video Coding) [1]. The MVC's prcimary target is 3D video compression for 3D display system, thus, key technology compared to 2D video compression is reducing inter-view correlation. It is noticed, however, that the current JMVM [2] does not effectively eliminate inter-view correlation so that there is still a room to improve coding efficiency. The proposed method utilizes similarity of interview residual signal and can provide an additional coding gain. It is claimed that up to 0.2dB PSNR gain with 1.4% bit-rate saving is obtained for three multi-view test sequences.

• Proceedings of the KSR Conference
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• 2003.10b
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• pp.259-264
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• 2003

Failure code system must include data of maintenance history, classification of failure, affective range and situation when failure occur. But the present failure code system have used a simple code system for classification to include only merchandise and tools. Advantageously, expansional standard code system that will be developed, it make that users can take steps of standardized overhaul and inspection as proposal maintain contents when failure occur or something wrong in vehicle of urban transit. Standardized failure codes must be developed and used that manufacturing companies and urban transit operating companies in order to give effect to maintenance works.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.1029-1030
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• 2008

The Scalable Video Coding(SVC) extention of H.264/AVC standard. SVC based temporal, spatial, snd qualty scalability of video bit streams. In this paper, we will develop C-model program and hardware circuits for the chip design of the SVC decoder. In order to acquire the flexibility of the circuit design and reliability of the hardware system development. In these development, we utilize the results of the C-model program to achieve the independencies of each sub-blocks and check the efficiencies of the circuit design results.

• IEIE Transactions on Smart Processing and Computing
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• v.3 no.6
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• pp.353-357
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• 2014

This paper, presents an efficient hardware architecture of high performance SVC(Scalable Video Coding). This platform uses dedicated hardware architecture to improve its performance. The architecture was prototyped in Verilog HDL and synthesized using the Synopsys Design Compiler with a 65nm standard cell library. At a clock frequency of 266MHz, This platform contains 2,500,000 logic gates and 750,000 memory gates. The performance of the platform is indicated by 30 frames/s of the SVC encoder Full HD($1920{\times}1080$), HD($1280{\times}720$), and D1($720{\times}480$) at 266MHz.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.4
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• pp.235-241
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• 2016

Compared to the former H.264 standard, the number of the prediction modes has highly increased in HEVC intra prediction. Compression efficiency and accurate prediction are significantly improved. However, the computational complexity increases as well. To solve this problem, this paper proposes the new scheme where not only prediction modes but also block partition candidate are early chosen. Compared to the original intra prediction in HEVC, the proposed scheme achieves about 38% reduction in processing cycles with a marginal loss in compression efficiency.

• Korean Journal of Microbiology
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• v.27 no.3
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• pp.259-264
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• 1989

The adherence of $^{3}H$-labeled oral streptococcal cells to protein-coated hydroxyapatite (HA) beads was studied by a standard adherence assay. The adherence equilibrium for S. mutans 10449 occured in about 2 hrs. The cell numbers adhering to SHA was 50% less than those on bare HA. Sailva from different subjects had varying effect on bacterial adherence. The use of saliva adsorbed with homologouis bacteria decreased S. mutans adherence by 38% ; this indicates the presence of salivary agglutinin in acquired pellicle formed on HA. Animal sera and BSA decreased S. sanguis adherence. BSA concentration as high as 10mg/ml caused up to 87% adherence inhibition. The desorption experiment of adhered bacteria confirmed the previous reports that the adhesive sites on HA beads for S. mutans were different from those for S. sanguis and that S. mutans could enhance the adherence of S. sanguis but not vice versa.

• Journal of information and communication convergence engineering
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• v.11 no.2
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• pp.118-123
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• 2013

This paper proposes an efficient hardware architecture for high efficiency video coding (HEVC), which is the next generation video compression standard. It adopts several new coding techniques to reduce the bit rate by about 50% compared with the previous one. Unlike the previous H.264/AVC 6-tap interpolation filter, in HEVC, a one-dimensional seven-tap and eight-tap filter is adopted for luma interpolation, but it also increases the complexity and gate area in hardware implementation. In this paper, we propose a parallel architecture to boost the interpolation performance, achieving a luma $4{\times}4$ block interpolation in 2-4 cycles. The proposed architecture contains shared operations reducing the gate count increased due to the parallel architecture. This makes the area efficiency better than the previous design, in the best case, with the performance improved by about 75.15%. It is synthesized with the MagnaChip $0.18{\mu}m$ library and can reach the maximum frequency of 200 MHz.