• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.10
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• pp.1845-1852
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• 2008

The key elements of inter prediction are motion estimation(ME) and motion compensation(MC). Motion estimation is to find the optimum motion vectors, not only by using a distance criteria like the SAD, but also by taking into account the resulting number of 비트s in the 비트 stream. Motion compensation is compensate for movement of blocks of current frame. Inter-prediction Encoding is always the main bottleneck in high-quality streaming applications. Therefore, in real-time streaming applications, dedicated hardware for executing Inter-prediction is required. In this paper, we studied a motion estimator(ME) for H.264/AVC. The designed motion estimator is based on 2-D systolic array and it connects processing elements for fast SAD(Sum of Absolute Difference) calculation in parallel. By providing different path for the upper and lower lesion of each reference data and adjusting the input sequence, consecutive calculation for motion estimation is executed without pipeline stall. With data reuse technique, it reduces memory access, and there is no extra delay for finding optimal partitions and motion vectors. The motion estimator supports variable-block size and takes 328 cycles for macro-block calculation. The proposed architecture is local memory-free different from paper [6] using local memory. This motion estimation encoder can be applicable to real-time video processing.

• Journal of Korea Multimedia Society
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• v.12 no.7
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• pp.922-928
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• 2009

In H.264 as the newest video standard, 9 modes are used in order to predict the signal values of a block composed with several pixels by intra prediction. From these process, H.264 can bring high compression ratio in the encoded signal but the use of total 9 modes can give the inefficiency of the increase of the complexity induced by the amount of operation processing or the number of searching which is applied to compare adjacent pixels. This paper proposes a simplification method of prediction mode for the intra-picture coding by considering subjective interest region. There are certain region being interested within a picture of the video sequence. This region requires better subjective picture quality than the other regions. The proposed method increases the simplification of prediction mode by providing just essential modes of total 9 modes for less interest regions compared with the interest region. It is possible to get the additional 11%$\sim$15% simplification of the prediction mode by the proposed method, compared with the conventional method which simplifies the prediction mode for all of the picture by using the prediction characteristics only.

• Journal of Broadcast Engineering
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• v.17 no.3
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• pp.480-490
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• 2012

When interpolating chrominance signal, the H.264/AVC standard uses linear interpolation. In this paper, we suggest more effective method that uses a high precision filter, 6-tap FIR filter, 2-tap linear filter for chroma interpolation. The experimental result shows that the proposed method achieves the BD-Rate decrease without the PSNR decrease compared with Jm11.0kta2.7. The maximum BD-rate improvements on Y component are 1.3%, those of Cb and Cr components are 19.8%, 25.0%, respectively. The average BD-rate improvements on Y component are 0.5%, those of Cb and Cr components are 6.1%, 6.9%, respectively.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.47 no.5
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• pp.165-174
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• 2010

The H.264/AVC standard obtained better performance than previous compression standards, but it also increased the computational complexity of CODEC simultaneously. Various techniques recently included at the KTA software developed by VCEG also were increasing its complexity. Especially adaptive interpolation filter has more complexity than two times due to development for coding efficiency. In this paper, we propose low-complexity filter bank to improve speed up of decoding and coding gain. We consists of filter bank of a fixed-simple filter for low-complexity and adaptive interpolation filter for high coding efficiency. Then we compensated using optimal filter at each macroblock-level or frame-level. Experimental results shows a similar coding efficiency compared to existing adaptive interpolation filter and decoding speed of approximately 12% of the entire decoder gained.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.4 s.316
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• pp.51-59
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• 2007

In this paper, we propose an efficient hardware architecture for H.264/AVC CAVLC (Context-based Adaptive Variable Length Coding) decoding which used for baseline profile and extended profile. Previous CAVLC architectures are consisted of five step block and each block gets effective bits from Controller block and Accumulator. If large number of non-zero coefficients exist, process for getting effective bits has to iterates many times. In order to reduce this unnecessary process, we propose two techniques, which combine five steps into four steps and reduce process to get efficiency bit by skipping addition step. By adopting these two techniques, the required processing time was reduced about 26% compared with previous architectures. It was designed in a hardware description language and total logic gate count was 16.83k using 0.18um standard cell library.

• Journal of Broadcast Engineering
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• v.13 no.3
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• pp.328-338
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• 2008

Multi-view video coding (MVC) based on H.264/AVC encodes multiple views efficiently by using a prediction scheme that exploits inter-view correlation among multiple views. However, with the increase of the number of views and use of inter-view prediction among views, total encoding time will be increased in multiview video coding. In this paper, we propose a fast mode decision using both MB(Macroblock)-based region segmentation information corresponding to each view in multiple views and global disparity vector among views in order to reduce encoding time. The proposed method achieves on average 40% reduction of total encoding time with the objective video quality degradation of about 0.04 dB peak signal-to-noise ratio (PSNR) by using joint multi-view video model (JMVM) 4.0 that is the reference software of the multiview video coding standard.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.46 no.4
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• pp.50-57
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• 2009

This paper presents a new model-based macroblock layer rate control algorithm for low bit rate video coding which generates output bits corresponding to a target bit budget. The H.264 standard uses various coding modes and optimization methods to improve the compression performance, which makes it difficult to control the generated traffic accurately in low bit rate environments. In the proposed scheme, we first estimate MAD values of macroblocks in a frame and define a target remaining bits using the estimated MAD values before encoding each macroblock. If a difference between the target value and the actual value is greater than a threshold value, the quantization parameter is adjusted to decrease the difference. It is shown by experimental results that the new algorithm can obtain more than 66% decrease of the difference between the target bits and the resulting bits for a frame with the PSNR performance better than that of the existing rate control algorithm.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.57-60
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• 2008

In this paper, we describe the technology about multiview video coding which is a hot issue in diqital video coding. A multiview video coding (MVC) is able to provide a free view point and 3-D effect, resulting that it gives more realism to users. Now, the MVC has been standardized as an amendment of H.264/AVC. In this paper, we present not only the MVC standard but also relevant techniques which were under consideration in the MVC standardization.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.1011-1012
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• 2006

In this paper, implementation process of standard platform for T-DMB Receiver in low-cost and small-size are following: First, implement SoC for 32 bit RISC CPU and 16 bit DSP, Hardware H.264 CODEC, Post Processor or Video Display, Audio Processor, I/O Device. Second, implement Real Time OS for flexible application. Third, propose simple architecture for interface with peripheral devices using one-chip processor.

• Proceedings of the KIEE Conference
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• 2001.07a
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• pp.264-266
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• 2001

We must consider resistance capacitance and their circuit connection condition for cable charging current test by IEC60265-1. According to their values and circuits, the ratio of applied voltage and transient recovery voltage are much different. This paper is convinced of TRV waves and proposes the optical circuit required at the standard via the simulation of all circuit conditions.