• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.10 s.352
• /
• pp.45-53
• /
• 2006

In this paper, we proposed a parallel hardware architecture for deblocking filter in K264/AVC. The deblocking filter has high efficiency in H.264/AVC, but it also has high computational complexity. For real time video processing, we chose a two 1-D parallel filter architecture, and tried to reduce memory access using dual-port SRAM. The proposed architecture has been described in Verilog-HDL and synthesized on Hynix 0.25um CMOS Cell Library using Synopsys Design Compiler. The hardware size was about 27.3K logic gates (without On-chip Memory) and the maximum operating frequency was 100Mhz. It consumes 258 clocks to process one macroblock, witch means it can process 47.8 HD1080P(1920pixel* 1080pixel) frames per second. It seems that it can be used for real time H.264/AVC encoding and decoding of various multimedia applications.

• The KIPS Transactions:PartA
• /
• v.15A no.1
• /
• pp.61-68
• /
• 2008

In this paper, we propose the VLSI design of Multi-Format Video Decoder (MFD) to support video codec standards such as MPEG-2, MPEG-4, H.264 and VC-1. The target of the proposed MFD is the Full HD (High Definition) video processing needed for the high-end D-TV SoC (System-on-Chip). The size of the design is reduced by sharing the common large-size resources such as the RISC processor and the on-chip memory among the different codecs. In addition, a detachable architecture is introduced in order to easily add or remove the codecs. The detachable architecture preserves the stability of the previously designed and verified codecs. The size of the design is about 2.4 M gates and the operating clock frequency is 225MHz in the Samsung 65nm process. The proposed MFD supports more than Full-HD (1080p@30fps) video decoding, and the largest number of video codec standards known so far.

• Proceedings of the Korean Society of Broadcast Engineers Conference
• /
• 2011.07a
• /
• pp.192-195
• /
• 2011

본 논문에서는 JCT-VC(Joint Collaboration Team on Video Coding)에서 표준화가 진행 중인 HEVC(High Efficiency Video Coding)의 Test Model 인 HM1.0과 현재 디지털 방송, 통신, 저장 매체 등 다양한 응용 분야에 사용되고 있는 범용 비디오 코덱들 간의 객관적, 주관적 측면에서의 부호화 성능을 비교한다. 이를 통해 HEVC의 현재 성능 수준에 대한 평가 결과를 보이고, 활용 가능성에 대해 결론을 맺는다. 비교 대상 코덱으로는 H.264/AVC 표준의 S/W 기반인 VideoLAN Project의 x264와 MPEG-2 표준으로 Harmonic사의 H/W기반의 최신형 실시간 인코더인 Electra8000을 사용하였다. 총 5개의 HD(1920x1080)영상에 대한 객관적 성능 비교 결과, HM1.0이 x264 대비 평균 44.93%의 BD-rate 감소와 평균 1.65%의 BD-PSNR 증가를 보였고, Electra8000에 대해서도 월등히 높은 성능차를 보였다. 주관적 화질 비교 결과 동일 PSNR 조건하에서 HM1.0이 범용 비디오 코덱들보다 주관적 화질이 유사하거나 좀 더 나음을 보였다.

• ETRI Journal
• /
• v.31 no.6
• /
• pp.784-794
• /
• 2009

We present a full HD (1080p) H.264/AVC High Profile hardware encoder based on fast motion estimation (ME). Most processing cycles are occupied with ME and use external memory access to fetch samples, which degrades the performance of the encoder. A novel approach to fast ME which uses shared multibank memory can solve these problems. The proposed pixel subsampling ME algorithm is suitable for fast motion vector searches for high-quality resolution images. The proposed algorithm achieves an 87.5% reduction of computational complexity compared with the full search algorithm in the JM reference software, while sustaining the video quality without any conspicuous PSNR loss. The usage amount of shared multibank memory between the coarse ME and fine ME blocks is 93.6%, which saves external memory access cycles and speeds up ME. It is feasible to perform the algorithm at a 270 MHz clock speed for 30 frame/s real-time full HD encoding. Its total gate count is 872k, and internal SRAM size is 41.8 kB.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.11
• /
• pp.77-82
• /
• 2008

H.264 is a video coding standard of ITU-T and ISO/IEC, and widely spreads its application due to its high compression ratio more than twice that of MPEG-2 and high image quality. It has different architecture depending on demands since it is a lied from small image of QVGA to large size of HD. In this paper, We propose a scalable architecture for intra-prediction of H.264 decoders. The proposed scheme has a scalable architecture that can accommodate up to 4 processing elements depending on performance demands and can reduce the number of access to memory using efficient memory management so as to be energy-efficient. We design the intra-prediction unit using Verilog-HDL and verily it by prototyping using an FPGA. The performance is analyzed using the results of design.

• Electronics and Telecommunications Trends
• /
• v.21 no.1 s.97
• /
• pp.25-34
• /
• 2006

H. 264 비디오 표준은 2005년 현재, MPEG-2를 대체하는 새로운 비디오 표준으로서세계 각국에서 신 개념 멀티미디어 서비스의 기본 기술로서 채택이 유력시 되고 있다.한국에서는 DMB 서비스를 위한 기본 비디오 기술로서 알려져 있는 H. 264는 미국 및유럽 등에서는 차세대 HD 서비스를 위한 비디오 코덱으로 받아 들여지고 있으며 HD급 H. 264 시스템 기술 경쟁이 날로 치열해지고 있는 상황이다. 본 논문에서는 HD급고화질 H. 264 기술에 대한 소개와 발전 동향을 설명하고 ETRI에서 독자 개발한 HD급H. 264 부호화기와 복호화기의 소개 및 성능에 대하여 소개하고자 한다.

• Electronics and Telecommunications Trends
• /
• v.23 no.1 s.109
• /
• pp.54-64
• /
• 2008

H.264 비디오 표준은 2005년 현재, MPEG-2를 대체하는 새로운 비디오 표준으로서 세계 각국에서 신 개념 멀티미디어 서비스의 기본 기술로서 채택이 유력시 되고 있다. 한국에서 DMB 서비스를 위한 기본 비디오 기술로서 알려져 있는 H.264는 미국 및 유럽 등에서는 차세대 HD 서비스를 위한 비디오 코덱으로 받아 들여지고 있으며 HD급 H.264 시스템 기술 경쟁이 날로 치열해지고 있는 상황이다. 본 논문에서는 HD급 H.264 기반 멀티미디어 시스템 기술에 대한 소개와 발전 동향을 설명하고 ETRI에서 독자 개발한 HD급 H.264 부호화기, 복호화기의 소개 및 성능에 대하여 소개하고자 한다.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.16 no.1
• /
• pp.119-126
• /
• 2012

H.264/AVC can use three transforms depending on types of residual data which are to be coded. H.264/AVC always executes $4{\times}4$ DCT transform. In $16{\times}16$ intra mode only, $4{\times}4$ Hadamard transform for luma DC coefficients and $2{\times}2$ Hadamard transform for chroma DC coefficients are performed additionally. Quantization is carried out to achieve further data compression after transform coding is completed. In this paper, the hardware implementation for DCT transform, Hadamard transform and quantization is studied. Especially, the proposed architecture adopting the pipeline technique can output a quantized result per clock cycle after 33-clock cycle latency. The proposed architecture is coded in Verilog-HDL and synthesized using Xilinx 7.1i ISE tool. The operating frequency is 106MHz at SPARTAN3S-1000. The designed IP can process maximum 33-frame at $1920{\times}1080$ HD resolution.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.12
• /
• pp.48-54
• /
• 2010

This paper presents a high-performance architecture of integer-pel motion estimation circuit for H.264 video CODEC. Full search algorithm guarantees the best results by examining all candidate blocks. However, the full search algorithm requires a huge amount of computation and data. Many fast search algorithms have been proposed to reduce the computational efforts. The disadvantage of these algorithms is that data access from or to memory is very irregular and data reuse is difficult. In this paper, we propose an efficient integer-pixel motion estimation algorithm and the circuit architecture to improve the processing speed and reduce the external memory bandwidth. The proposed circuit supports seven kinds of variable block sizes and generates 41 motion vectors. We described the proposed high-performance motion estimation circuit at R1L and verified its operation on FPGA board. The circuit synthesized by using l30nm CMOS standard cell library processes 139.8 1080HD ($1,920{\times}1,088$) image frames per second and supports up to H.264 level 5.1.

• Proceedings of the IEEK Conference
• /
• 2008.06a
• /
• pp.409-410
• /
• 2008

This paper presents nonlinear and parallel design for synchronous pipelining in IP-based H.264 decoder implementation. Since H.264 decoder includes the dataflow of feedback loop, the data dependency requires one NOP stage per pipelining latency to drop the throughput into 1/2. Further, it is found that, in execution time, the stage scheduled for MC is more occupied than that for CAVLD/ITQ/DF. The less efficient stage would be improved by nonlinear scheduling, while the fully-utilized stage could be accelerated by parallel scheduling of IP. The optimization yields 3 nonlinear {CAVLD&ITQ}|3 parallel (MC/IP&Rec.)| 3 nonlinear {DF} pipelined architecture for IP-based H.264 decoder. In experiments, the nonlinear and parallel pipelined H.264 decoder, including existing IPs, could deal with full HD video at 41.86MHz, in real time processing.