• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.430-442
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• 2013

This paper presents a fast multi-reference frame integer motion estimator for H.264/AVC. The proposed system uses the previously proposed fast multi-reference frame algorithm. The previously proposed algorithm executes a full search area motion estimation in reference frames 0 and 1. After that, the search areas of motion estimation in reference frames 2, 3 and 4 are minimized by a linear relationship between the motion vector and the distances from the current frame to the reference frames. For hardware implementation, the modified algorithm optimizes the search area, reduces the overlapping search area and modifies a division equation. Because the search area is reduced, the amount of computation is reduced by 58.7%. In experimental results, the modified algorithm shows an increase of bit-rate in 0.36% when compared with the five reference frame standard. The pipeline structure and the memory controller are also adopted for real-time video encoding. The proposed system is implemented using 0.13 um CMOS technology, and the gate count is 1089K with 6.50 KB of internal SRAM. It can encode a Full HD video ($1920{\times}1080P@30Hz$) in real-time at a 135 MHz clock speed with 5 reference frames.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.102-116
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• 2009

There have been lots of researches for H.264/AVC performance enhancement on a multi-core processor. The enhancement has been performed through parallelization methods. Parallelization methods can be classified into a task-level parallelization method and a data level parallelization method. A task-level parallelization method for H.264/AVC decoder is implemented by dividing H.264/AVC decoder algorithms into pipeline stages. However, it is not suitable for complex and large bitstreams due to poor load-balancing. Considering load-balancing and performance scalability, we propose a horizontal data level parallelization method for H.264/AVC decoder in such a way that threads are assigned to macroblock lines. We develop a mathematical performance expectation model for the proposed parallelization methods. For evaluation of the mathematical performance expectation, we measured the performance with JM 13.2 reference software on ARM11 MPCore Evaluation Board. The cycle-accurate measurement with SoCDesigner Co-verification Environment showed that expected performance and performance scalability of the proposed parallelization method was accurate in relatively high level

• IEIE Transactions on Smart Processing and Computing
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• v.3 no.6
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• pp.353-357
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• 2014

This paper, presents an efficient hardware architecture of high performance SVC(Scalable Video Coding). This platform uses dedicated hardware architecture to improve its performance. The architecture was prototyped in Verilog HDL and synthesized using the Synopsys Design Compiler with a 65nm standard cell library. At a clock frequency of 266MHz, This platform contains 2,500,000 logic gates and 750,000 memory gates. The performance of the platform is indicated by 30 frames/s of the SVC encoder Full HD($1920{\times}1080$), HD($1280{\times}720$), and D1($720{\times}480$) at 266MHz.

• IEMEK Journal of Embedded Systems and Applications
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• v.3 no.4
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• pp.193-197
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• 2008

In today's Pay TV market, the importance of TPS for Pay TV operators is increasing rapidly. IP Hybrid services are essential for satellite broadcasters. This paper explains the various digital satellite broadcasting service trend, especially IP based hybrid service approach of satellite broadcasters(BskyB, CanalSat, DirecTV, etc.). Also this paper introduces SkyLife IP hybrid business approach to achieve a strong leadership in Pay TV market and related IP convergence market in Korea.

• The Journal of the Korea Contents Association
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• v.12 no.6
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• pp.78-91
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• 2012

The Terrestrial DTV service compliant with ATSC has been advancing for years. In KBA(Korean Broadcasters Association), a multi-channel service was broadcasted on air during the period of the 2006 FIFA World Cup Germany with the various type of MMS(Multi Mode Service) using MPEG-2 encoding method. MMS Service can provides not only one HD channel but also serveral additional services within 6MHz bandwidth. Using digital video compression technology(MPEG-2), many various programs such as HDTV, SDTV, Audio and Data are able to be transmitted within the same bandwidth. From November 2009, KBS has been preparing an advanced MMS service, 'Korea-View' which has both methods of encoding, MPEG-2 and H.264 that is compliant ATSC mobile standard, A/153. Korea-View is a kind of multi-channel broadcast service to provide one HD and 3 SD programs with the bandwidth of 6MHz. Terrestrial multi-channel service is required to focuse on expanding viewer service. Such Terrestrial multi-channel services will contribute to transferring to digital broadcasting and to extending the viewers' welfare. Due to advances in digital technology, Pay-TV channels has increased to hundreds. Even though digital switchover is being proceeded, terrestrial broadcasters have been unable to deliver multi-channel services. In this paper, technical features and differences of MMS and Koreaview will be analyzed regarding terrestrial multi-channel broadcasting services, and the politic direction will be proposed in accordance with introduction of future service.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.6
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• pp.6-15
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• 2009

In this paper, a new 4-way search window is designed for the high-performance 2D PE architecture in H.264 Motion Estimation(ME) to improve the memory bandwidth. While existing 2D PE architectures reuse the overlapped data of adjacent search windows scanned in 1 or 3-way, the new window utilizes the overlapped data of adjacent search windows as well as adjacent multiple scanning (window) paths to enhance the reusage of retrieved search window data. In order to scan adjacent windows and multiple paths instead of single raster and zigzag scanning of adjacent windows, bidirectional row and column window scanning results in the 4-way(up. down, left, right) search window. The proposed 4-way search window could improve the reuse of overlapped window data to reduce the redundancy access factor by 3.1, though the 1/3-way search window redundantly requires $7.7{\sim}11$ times of data retrieval. Thus, the new 4-way search window scheme enhances the memory bandwidth by $70{\sim}58%$ compared with 1/3-way search window. The 2D PE architecture in H.264 ME for 4-way search window consists of $16{\times}16$ pe array. computing the absolute difference between current and reference frames, and $5{\times}16$ reusage array, storing the overlapped data of adjacent search windows and multiple scanning paths. The reference data could be loaded upward and downward into the new 2D PE depending on scanning direction, and the reusage array is combined with the pe array rotating left as well as right to utilize the overlapped data of adjacent multiple scan paths. In experiments, the new implementation of 4-way search window on Magnachip 0.18um could deal with the HD($1280{\times}720$) video of 1 reference frame, $48{\times}48$ search area and $16{\times}16$ macroblock by 30fps at 149.25MHz.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2011.07a
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• pp.180-183
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• 2011

본 논문에서는 HEVC(High Efficiency Video Coding) 부호화기에서 사용되는 TU(Transform Unit) 분할이 깊이에 따라 속도와 화질과 압축률에 미치는 영향을 분석한다. 현재 HD 영상의 표준 부호화기로 사용되던 H.264/AVC 를 대신할 차세대 부호화기인 HEVC 에 대한 표준화 작업이 이루어지고 있으며 이러한 HEVC 부호화기의 특징 중 하나로 영상 압축 시 CU, PU, TU 로 세분화 된 단위를 사용한다는 점을 들 수 있다. HEVC의 reference software 인 HM 의 경우 기존 H.264/AVC 에 비하여 UHD 영상에서 최대 40%에 가까운 비트 절감률을 보이지만 최적화가 이루어지지 않아 실시간 부호화에는 적합하지 않은 속도를 보인다. HM 에서는 각 CU 나 TU 에 대하여 quadtree 형식으로 분할하여 부호화를 수행한 후 최적의 분할 형태를 취하는 방식을 사용하기 때문에 많은 시간을 소요하게 되며 분할되는 깊이에 비례하여 기하급수적으로 속도가 느려지게 된다. 본 논문에서는 TU 가 분할되는 깊이가 부호화 화질과 속도에 어느 정도 영향을 미치는지를 분석하고 화질 손상을 최소화 하는 최적의 TU 분할 깊이를 제안하여 보기로 한다.

• Journal of Aerospace System Engineering
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• v.13 no.2
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• pp.10-18
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• 2019

In this paper, we present the results of a developed LTE/Wi-Fi-based video transmission system which can be applied in small unmanned aerial vehicles of 25kg or less. The developed video transmission system comprised of airborne datalink terminal, ground datalink terminal, and used LTE and Wi-Fi wireless data communication technologies to transmit videos of resolution higher than HD (720p/30fps, 1080p/30fps) taken by small UAV. The airborne device is designed to efficiently transmit real-time streaming video through the incorporation of H.264 video processing board. Ground tests and evaluation indicated the possibility of the developed system to transmit real-time videos from close distance in regards to non-line-of-sight area.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.4 s.316
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• pp.51-59
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• 2007

In this paper, we propose an efficient hardware architecture for H.264/AVC CAVLC (Context-based Adaptive Variable Length Coding) decoding which used for baseline profile and extended profile. Previous CAVLC architectures are consisted of five step block and each block gets effective bits from Controller block and Accumulator. If large number of non-zero coefficients exist, process for getting effective bits has to iterates many times. In order to reduce this unnecessary process, we propose two techniques, which combine five steps into four steps and reduce process to get efficiency bit by skipping addition step. By adopting these two techniques, the required processing time was reduced about 26% compared with previous architectures. It was designed in a hardware description language and total logic gate count was 16.83k using 0.18um standard cell library.

• Journal of Broadcast Engineering
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• v.20 no.3
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• pp.388-397
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• 2015

High Efficiency Video Coding (HEVC)/H.265 is a new video coding standard which is known as high compression ratio compared to the previous standard, Advanced Video Coding (AVC)/H.264. Due to achievement of high efficiency, HEVC sacrifices the time complexity. To apply HEVC to the market applications, one of the key requirements is the fast encoding. To achieve the fast encoding, exploiting thread-level parallelism is widely chosen mechanism since multi-threading is commonly supported based on the multi-core computer architecture. In this paper, we implement both the Tile-level parallelism and the Frame-level parallelism for HEVC encoding on multi-core platform. Based on the implementation, we present two approaches in combining the Tile-level parallelism with Frame-level parallelism. The first approach creates the fixed number of tile per frame while the second approach creates the number of tile per frame adaptively according to the number of frame in parallel and the number of available worker threads. Experimental results show that both improves the parallel scalability compared to the one that use only tile-level parallelism and the second approach achieves good trade-off between parallel scalability and coding efficiency for both Full-HD (1080 x 1920) and 4K UHD (3840 x 2160) sequences.