• Transactions of the Korean hydrogen and new energy society
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• v.8 no.4
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• pp.145-154
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• 1997

The $H_2$ and $H_2S$ sensing characteristics of Pd and Pd-Rh gate MOS sensor and the effect of Pd deposition condition on the hydrogen sensing performance of Pd gate MOS sensor was investigated. The increase of rf power and deposition temperature led to the decrease in the sensitivity and the initial response rate. The deposition temperature gave more effects on the decrease of the sensitivity and the initial response rate than the rf power. The sensitivity of Pd-Rh sensor gave better performance than pure Pd sensor. As the concentration of Rh in the gate increased, the sensitivity decreased. For Pd-Rh sensor, the sensitivity to $H_2$ was higher than that to $H_2S$. It was demonstrated that rf power, deposition temperature had an important role in the sensor performance.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.7
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• pp.1393-1398
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• 2009

Conventionally, etching is first considered for microelectronics fabrication process and is specially important in process of a-Si:H thin film transistor for LCD. In this paper, we stabilize properties of device by development of wet and dry etching process. The a-Si:H TFTs of this paper is inverted staggered type. The gate electrode is lower part. The gate electrode is formed by patterning with length of 8 ${\mu}$m${\sim}$16 ${\mu}$m and width of 80${\sim}$200 ${\mu}$m after depositing with gate electrode (Cr) 1500 ${\AA}$under coming 7059 glass substrate. We have fabricated a-SiN:H, conductor, etch-stopper and photo resistor on gate electrode in sequence, respectively. The thickness of these thin films is formed with a-SiN:H (2000 ${\mu}$m), a-Si:H(2000 ${\mu}$m) and n+a-Si:H (500 ${\mu}$m), We have deposited n-a-Si:H, NPR(Negative Photo Resister) layer after forming pattern of Cr gate electrode by etch-stopper pattern. The NPR layer by inverting pattern of upper gate electrode is patterned and the n+a-Si:H layer is etched by the NPR pattern. The NPR layer is removed. After Cr layer is deposited and patterned, the source-drain electrode is formed. In the fabricated TFT, the most frequent problems are over and under etching in etching process. We were able to improve properties of device by strict criterion on wet, dry etching and cleaning process.

• Proceedings of the Korea Water Resources Association Conference
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• 2006.05a
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• pp.546-551
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• 2006

It considered the population decrease and becoming older in age of the Rural area and operates by unmaned-non power which self-controlled gate developed. The operational principal used a buoyancy and when water level in the canal arrived to the set water level, in order for gate to be opened. The plate in order to fix to the shape in the canal which begs, it did in the quadrilateral and the rainfall it is sour intensively, canal bank comfort plate in order to ascend completely, it designed. The result which establishes Self-controlled gate, the gate upstream 1km until degree there was water level synergistic effect. It developed 4 as the research project and it established in Ah San city, and it establishes the Self-controlled gate of $B3.2m{\times}H2.4m$ size in Damyang and 100ha it does water supply in the rice field.

• Proceedings of the KIEE Conference
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• 1990.07a
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• pp.439-442
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• 1990

GaAs MESFETs with the submicron gat are fabricated. $G_{m,mas}$ = 195mS/mm with the $0.5{\mu}m$ gate length and $G_{m,mas}$ = 170mS/mm with the $0.6{\mu}m$ gate lenth. $f_{mas}$ = 7GHz with the $1.5{\mu}m$ gate length and the $120{\mu}m$ gate width. We can estimate that $f_{mas}$ = 15GHz with $0.6{\mu}m$ gate length and that $f_{mas}$ = 18 ${\sim}$ 20GHz with the $0.5{\mu}m$ gate length.

• Proceedings of the KIEE Conference
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• 1995.07a
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• pp.325-327
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• 1995

A new gate drive circuit of classic converter for a switched reluctance motor is presented. Conventional gate drive circuit usually consists of the isolated power supplies and signal transferring devices for isolation, such as photo coupler, pulse transformer, and gate drive chips. The proposed gate drive circuit consists of resistors, capacitors, and zenor diodes without isolated power supplies, that make the drive circuit simple and reduce the material cost. The operational modes are classified and analyzed. The characteristics of the phase current and the gate signal of upper switches is investigated with the variation of duty ratio through the experiments.

• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 2003.04a
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• pp.33-39
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• 2003

Injection molding is widely used in producing various plastic parts due to its high productivity and the demand for high precision injection molded products is ever increasing. To achieve successful product quality and precision, the design of gating and runner systems in the injection mold is very important since it directly influences melt flow into the cavity. Some defects such as weld lines and overpacking can be effectively controlled with proper selection of gate locations. In the present study, the design of gate locations in injection molding of a dashboard for automobiles was carried out with CAMPmold, a PC-based simulation system for injection molding. A dummy runner was developed to simulate a runner system in order to increase the efficiency of the analysis. The numbers and locations of gates were varied in the present investigation as that an acceptable design was obtained in terms of reduced maximum pressure and clamping force.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.04a
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• pp.187-190
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• 2000

We fabricated general photo diode, surface etched photo diode and floating gate MOSFET by CMOS process. In a design stage, we expect that surface etched photo diode will be improved as to photo sensitivity. However, because the surface of silicon was damaged in etching process, the surface etched diode had a high dark current as well as low photo current level. Finally, we examined the current-voltage properties for the floating gate MOSFET on n-well and confirmed that the device can be act as an efficient photo-sensor. The floating gate MOSFET was operated in parasitic bipolar transistor mode.

• Electrical & Electronic Materials
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• v.9 no.3
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• pp.277-283
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• 1996

The temperature dependent characteristics of hydrogenerated amorphous silcon thin film transistor (a-Si:H TFT) with a bottom gate of N-Type <100> Si wafer were investigated. Drain current on the hysteresis characteristic curve showed an exponential variation. Hysteresis area of TFT increased with the gate voltage increased and decreased with the small gate voltage. According to the variation of gate voltages, drain current of TFT increased by temperature increase, and hysteresis characteristics mainly depended on the temperature increase. The hysteresis current showed negative characteristics curve over 383K. The hysteresis occurance area and the differences of forward and reverse sweep were increased at the higher temperature. Hysteresis current of I$_{d}$(on/off) ratio decreased at the lower temperature and increased at the higher temperature.e.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.101-104
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• 2008

Too high stress of the bottom Mo layer of the gate line is thought to be the main reason for H-line mura. H-Line mura is eliminated effectively by changing the gate line metal structure from Mo/AlNd/Mo to AlNd/Mo. The new structure does not influence the panel's electrical characteristics.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.3
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• pp.139-144
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• 2003

We report the results of extensive mixed mode simulations and theoretical analysis to quantify the contribution of the edge direct tunneling (EDT) current on the total gate leakage current of 80nm NMOSFET with SiO2 gate dielectric. It is shown that EDT has a profound impact on basic analog circuit building blocks such as sample-hold (S/H) circuit and the current mirror circuit. A transistor design methodology with zero gate-source/drain overlap is proposed to mitigate the EDT effect. This results in lower voltage droop in S/H application and better current matching in current mirror application. It is demonstrated that decreasing the overlap length also improves the basic analog circuit performance metrics of the transistor. The transistor with zero gate-source/drain overlap, results in better transconductance, input resistance, output resistance, intrinsic gain and unity gain transition frequency.